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Low profile semiconductor die carrier 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/02
출원번호 US-0482000 (1995-06-07)
발명자 / 주소
  • Mosley Joseph M.
  • Portuondo Maria M.
  • Taylor Drew L.
출원인 / 주소
  • The Panda Project
대리인 / 주소
    Morgan, Lewis & Bockius LLP
인용정보 피인용 횟수 : 25  인용 특허 : 52

초록

A semiconductor die carrier configured to be secured to a printed circuit board includes an insulative package for housing a semiconductor die. The insulative package has a top surface, a bottom surface, and a plurality of side surfaces coupling the top surface and the bottom surface. At least one r

대표청구항

[ What is claimed is:] [1.] A semiconductor die carrier configured to be secured to a printed circuit board having a first side and a second side opposite to the first side, the semiconductor die carrier comprising:a housing for a semiconductor die, the housing having a top surface, a bottom surface

이 특허에 인용된 특허 (52)

  1. Frei John K. (Mesa AZ) Brice-Heames Kenneth (Mesa AZ), Apparatus for adapting semiconductor die pads and method therefor.
  2. Crane ; Jr. Stanford W. (Boca Raton FL) Portuondo Maria M. (Delray Beach FL), Apparatus having inner layers supporting surface-mount components.
  3. Hundt Michael J. (Double Oak TX), Circuit assembly having interposer lead frame.
  4. Sucheski Matthew M. (Harrisburg PA) Barkus Lee A. (Millersburg PA), Coaxial contact element.
  5. Kochanski Ronald P. (Arlington Heights IL) Schmidt Detlef W. (Schaumburg IL), Device with captivate chip capacitor devices and method of making the same.
  6. Gatto Donald F. (Sunrise FL) Milciunas Juan (Ft. Lauderdale FL), Dual electronic component assembly.
  7. Kondo Mitsuhiro (Oogaki JPX) Watanabe Osamu (Oogaki JPX), Encapsulated semiconductor device with bridge sealed lead frame.
  8. Sugimoto Masahiro (Yokosuka JPX) Wakasugi Yasumasa (Kawasaki JPX) Harada Shigeki (Kawasaki JPX), Heatsink package for flip-chip IC.
  9. Shaheen Joseph M. (La Habra CA) Yamaguchi James S. (Lake Forest CA), Hermetic organic/inorganic interconnection substrate for hybrid circuit manufacture.
  10. Frankeny, Jerome A.; Frankeny, Richard F.; Haj-Ali-Ahmadi, Javad; Hermann, Karl; Imken, Ronald L., High density interconnect strip.
  11. Desai Kishor V. (Vestal NY) Macek Thomas G. (Endicott NY) Patel Maganlal S. (Endicott NY) Thomas Edwin L. (Apalachin NY), High density, separable connector and contact for use therein.
  12. Sugano Toshio (Kodaira JPX) Tsukui Seiichiro (Kawagoe JPX), High packing density module board and electronic device having such module board.
  13. Boucard Michel R. J. (Tournefeuille FRX) Francois Thirion C. (Auterive FRX), Housing for an electronic circuit.
  14. Salera Edmond A. (Santa Barbara CA), Hybrid microelectronic circuit package.
  15. Krumme John F. (Woodside CA) Hodgson Darel E. (Palo Alto CA), Integrated circuit package and seal therefor.
  16. Tukamoto Takashi (Suwa JPX) Abe Sachiyuki (Suwa JPX) Yabushita Tetsuo (Suwa JPX) Hayashi Yoshimitsu (Suwa JPX), Integrated circuit package for flexible computer system alternative architectures.
  17. Papageorge Marc V. (Boca Raton FL) Freyman Bruce J. (Boca Raton FL) Juskey Frank J. (Coral Spring FL) Thome John R. (Palatine IL), Integrated circuit package having a face-to-face IC chip arrangement.
  18. Nelson Gregory H. (Gilbert AZ) Lebow Sanford (Westlake CA) Nogavich Eugene (Gilbert AZ), Interconnect device and method of manufacture thereof.
  19. Masayuki Watanabe (Yokohama JPX) Toshio Sugano (Kokubunji JPX) Seiichiro Tsukui (Komoro JPX) Takashi Ono (Akita JPX) Yoshiaki Wakashima (Kawasaki JPX), Lead connections means for stacked tab packaged IC chips.
  20. Shaffer Howard R. (Millersburg PA), Limited insertion force contact terminals and connectors.
  21. Krum Alvin L. (Huntington Beach CA) Conklin Charles W. (Huntington Beach CA), Low resistance electrical interconnection for synchronous rectifiers.
  22. Gregoire George D. (9927 Aviary Dr. San Diego CA 92131), Method and apparatus for making printed circuit boards.
  23. Kobayashi Yasushi (Kamikodanaka JPX) Kogure Seiji (Nakahara JPX), Method for encapsulting IC chip.
  24. Gregoire George D. (9927 Aviary Dr. San Diego CA 92131), Method for making printed circuit boards.
  25. Hingorany Prem R. (Broomfield CO), Method of manufacture power hybrid microcircuit.
  26. Crane ; Jr. Stanford W. (Boca Raton FL) Portuondo Maria M. (Delray Beach FL), Method of manufacturing a semiconductor chip carrier affording a high-density external interface.
  27. Crane ; Jr. Stanford W. (Boca Raton FL) Portuondo Maria M. (Delray Beach FL), Method of manufacturing an apparatus having inner layers supporting surface-mount components.
  28. Gregoire George D. (San Diego CA), Method of mounting a surface-mountable IC to a converter board.
  29. Gates ; Jr. Louis E. (Westlake Village CA) Kamensky Albert (Redondo Beach CA) Devendorf Don C. (Los Angeles CA), Microelectronic package.
  30. Reylek Robert S. (St. Paul MN) Thompson Kenneth C. (St. Paul MN), Miniature multiple conductor electrical connector.
  31. Taniuchi Kenjiro (Kawasaki JPX) Miyazawa Hideo (Kawasaki JPX) Ishikawa Kouji (Kawasaki JPX) Watanabe Kouji (Kawasaki JPX), Mounting device for mounting an electronic device on a substrate by the surface mounting technology.
  32. Martens John D. (Plano TX) Ammon J. Preston (Dallas TX), Multi row high density connector.
  33. Feng Bai-Cwo (Tarrytown NY) Feng George C. (Fishkill NY) McMaster Richard H. (Wappingers Falls NY), Multi-layer package incorporating a recessed cavity for a semiconductor chip.
  34. Hirano Naohiko (Yokohama JPX), Multilayer package.
  35. Tillotson John (Southfield MI), Multiple contact header assembly.
  36. Selinko George J. (Lighthouse Point FL), Non-hermetically sealed stackable chip carrier package.
  37. Ingram Arthur J. (Allentown PA) Weingrod Irving (Allentown PA), Package for semiconductor integrated circuits.
  38. Buck Jonathan E. (Harrisburg PA) Rose William H. (Harrisburg PA), Paired contact electrical connector system.
  39. Shirling David J. (Waterbury CT), Pin grid array having seperate posts and socket contacts.
  40. Kohno Ryuji (Ibaraki JPX) Nishimura Asao (Ushiku JPX) Kitano Makoto (Tsuchiura JPX) Yaguchi Akihiro (Ibaraki JPX) Yoneda Nae (Ibaraki JPX), Plastic-molded-type semiconductor device.
  41. Sakemi Shouzi (Fukuoka JPX) Sakai Tadahiko (Fukuoka JPX), Printed circuit board.
  42. Ammon J. Preston (Dallas TX) Weaver Harry R. (Dallas TX) Evans Evan J. (Plano TX), Printed circuit board finger connector.
  43. Hashemi Seyed H. (Austin TX) Olla Michael A. (Austin TX) Parker John C. (Round Rock TX), Process for manufacturing a stacked multiple leadframe semiconductor package using an alignment template.
  44. Utunomiya Jiro (Tokyo JPX) Iida Saburo (Tokyo JPX) Sibuya Hitosi (Tokyo JPX) Kusaba Kazunori (Tokyo JPX) Narumi Isao (Tokyo JPX), Process of assembling terminal structure.
  45. Brown Candice H. (San Jose CA), Process of making a semiconductor device having parallel leads directly connected perpendicular to integrated circuit la.
  46. Crane ; Jr. Stanford W. (Boca Raton FL) Portuondo Maria M. (Delray Beach FL), Semiconductor chip carrier affording a high-density external interface.
  47. Arima Hideo (Yokohama JPX) Takeda Kenji (Kamakura JPX) Yamamura Hideho (Yokohama JPX) Kobayashi Fumiyuki (Sagamihara JPX), Semiconductor chip carrier, module having same chip carrier mounted therein, and electronic device incorporating same mo.
  48. Kohara Masanobu (Itami JPX) Kondo Takashi (Itami JPX) Yama Yomiyuki (Itami JPX), Semiconductor device and package.
  49. Jurista Thomas M. (Vestal NY) Mantilla Osvaldo A. (Endicott NY), Sequential Connecting device.
  50. Dutta Vivek B. (Cupertino CA) Demmin Jeffrey C. (Mt. View CA) DiOrio Mark L. (Cupertino CA) Ewanich Jon T. (Cupertino CA), Stadium-stepped package for an integrated circuit with air dielectric.
  51. Juskey Frank J. (Coral Springs FL) Suppelsa Anthony B. (Coral Springs FL), Thermally conductive integrated circuit package with radio frequency shielding.
  52. Nicewarner ; Jr. Earl R. (Gaithersburg MD), Three-dimensional integrated circuit package.

이 특허를 인용한 특허 (25)

  1. Bolken, Todd O.; Peters, David L., Apparatus for encapsulating a multi-chip substrate array.
  2. Bolken,Todd O.; Peters,David L., Apparatus for encapsulating a multi-chip substrate array.
  3. Kim Dong-You,KRX, Bottom lead frame and bottom lead semiconductor package using the same.
  4. Andrade,Thomas L., Capacitive sensor system with improved capacitance measuring sensitivity.
  5. Glenn Thomas P., Electrostatic discharge protection package and method.
  6. Knapp, James; St. Germain, Stephen, Integrated circuit and laminated leadframe package.
  7. Hatano Hiromitsu,JPX, Integrated circuit package having stepped terminals.
  8. Michii, Kazunari, Integrated circuits substrate.
  9. Bolken, Todd O.; Peters, David L., Method and apparatus for encapsulating a multi-chip substrate array.
  10. Bolken, Todd O.; Peters, David L., Method for encapsulating a multi-chip substrate array.
  11. Gall Peter J., Method of fabricating integrated circuit package with opening allowing access to die.
  12. Miyaki, Yoshinori; Suzuki, Hiromichi, Method of packaging a semiconductor device having gull-wing leads with thinner end portions.
  13. Chen, Wen-Yen, Multi-functional memory chip connector.
  14. Egitto, Frank D.; Farquhar, Donald S.; Markovich, Voya R.; Poliks, Mark D.; Powell, Douglas O., Multi-layered interconnect structure using liquid crystalline polymer dielectric.
  15. Egitto, Frank D.; Farquhar, Donald S.; Markovich, Voya R.; Poliks, Mark D.; Powell, Douglas O., Multi-layered interconnect structure using liquid crystalline polymer dielectric.
  16. Egitto, Frank D.; Farquhar, Donald S.; Markovich, Voya R.; Poliks, Mark D.; Powell, Douglas O., Multi-layered interconnect structure using liquid crystalline polymer dielectric.
  17. Egitto,Frank D.; Farquhar,Donald S.; Markovich,Voya R.; Poliks,Mark D.; Powell,Douglas O., Multi-layered interconnect structure using liquid crystalline polymer dielectric.
  18. Hamzehdoost Ahmad B. ; Huang Chin-Ching, Printed circuit board layout to minimize the clock delay caused by mismatch in length of metal lines and enhance the thermal performance of microelectronics packages via conduction through the packag.
  19. Crane, Jr., Stanford W.; Portuondo, Maria M., Semiconductor chip carrier affording a high-density external interface.
  20. Crane, Jr.,Stanford W.; Portuondo,Maria M., Semiconductor chip carrier affording a high-density external interface.
  21. Crane ; Jr. Stanford W. ; Portuondo Maria M., Semiconductor chip carrier including an interconnect component interface.
  22. Miyaki, Yoshinori; Suzuki, Hiromichi, Semiconductor device.
  23. Miyaki, Yoshinori; Suzuki, Hiromichi, Semiconductor device.
  24. Alvarez, Robert; Moehle, Paul R.; Kellher, Harold T., Stabilizer/spacer for semiconductor device.
  25. Andrade,Thomas L., Surface capacitance sensor system using buried stimulus electrode.
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