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Partial broadcast method in parallel computer and a parallel computer suitable therefor 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-015/163
  • G06F-015/173
출원번호 US-0916630 (1992-07-22)
우선권정보 JP-0180743 (1991-07-22)
발명자 / 주소
  • Ogata Yasuhiro,JPX
  • Nakagoshi Junji,JPX
  • Hamanaka Naoki,JPX
  • Chiba Hiroyuki,JPX
  • Shutoh Shinichi,JPX
  • Higuchi Tatsuo,JPX
  • Takeuchi Shigeo,JPX
  • Toba Taturu,JPX
  • Tanaka Teruo,JPX
출원인 / 주소
  • Hitachi VLSI Engineering Corporation, JPX
대리인 / 주소
    Antonelli, Terry, Stout & Kraus, LLP
인용정보 피인용 횟수 : 40  인용 특허 : 58

초록

In order to determine a transfer path of a message to a receiving-end processor group, a processor includes a routing bit generation circuit, and an exchange switch includes partial broadcast path control circuits and a path control information alteration circuit. In order to define the range of a r

대표청구항

[ What is claimed is:] [12.] A parallel computer including a plurality of processors and a network for connecting said processors, said network including a plurality of partial networks for transferring messages therebetween, said parallel computer comprises:a plurality of both input and output term

이 특허에 인용된 특허 (58)

  1. McAulay Alastair D. (Dallas TX), A plurality of optical crossbar switches and exchange switches for parallel processor computer.
  2. Frey ; Jr. Alexander H. (Pasadena CA) Gould Joel M. (Norwood MA) Higgins ; Jr. Charles M. (Baton Rouge LA), Adaptive routing in a parallel computing system.
  3. Olson Jeffrey J. (Boulder CO) Peck Stephen R. (Boulder CO) Seaton David P. (Boulder CO), Alternate routing arrangement.
  4. Hardell ; Jr. William R. (Austin TX) Henson ; Jr. James D. (Austin TX) Mitchell Oscar R. (Pflugerville TX), Apparatus and method for booting a multiple processor system having a global/local memory architecture.
  5. Carn Ronald C. (Millis MA) Metz Donald R. (Ashburnham MA) Zagame Steven P. (Boylston MA) Kirk Robert C. (Boylston MA) Kent Allan R. (Arlington MA) Read Harold A. (Burlin MA) Henry Barry A. (Penacook , Blocking message transmission or signaling error in response to message addresses in a computer interconnect coupler for.
  6. Olnowich Howard T. (Endwell NY) Lusch Robert F. (Vestal NY) Jabusch John D. (Endwell NY), Broadcast/switching apparatus for executing broadcast/multi-cast transfers over unbuffered asynchronous switching networ.
  7. DeMesa ; III Nicanor P. (North Stonington CT) Laabs John E. (North Stonington CT), Bus collision avoidance system for distributed network data processing communications system.
  8. Chao Hung-Hsiang J. (Lincroft NJ), Crosspoint matrix switching element for a packet switch.
  9. Frieder Gideon (Williamsville NY) Hughes David T. (Amherst NY) Kline Mark H. (Williamsville NY) Liebel ; Jr. John T. (Williamsville NY) Meier David P. (Orchard Park NY) Wolff Edward A. (Tonawanda NY), Data processing system.
  10. Kennedy Barry (Santa Ana CA), Distributed multi-processor boot system for booting each processor in sequence including watchdog timer for resetting ea.
  11. Works George A. (Stow MA), Distributed signal processing system.
  12. Ing-Simmons Nicholas K. (Oakley TX GB2) Guttag Karl M. (Missouri City TX) Gove Robert J. (Plano TX) Balmer Keith (Bedford GB2), Dual mode SIMD/MIMD processor providing reuse of MIMD instruction memories as data memories when operating in SIMD mode.
  13. Akata Masao (Tokyo JPX), Dual port memory buffers and a time slot scheduler for an ATM space division switching system.
  14. Brown Norman P. (Tomball TX) Williams ; Jr. James D. (Cypress TX) Clary Donald P. (Houston TX) Nuckols James H. (Houston TX), External boot information loading of a personal computer.
  15. Tseung, Lawrence C. N., Guaranteed reliable broadcast network.
  16. Amada Eiichi (Kodaira JPX), High-speed packet switching using a space division optical switch.
  17. Ikeda Kazuhiko (Yamato JPX) Sakai Satoru (Kawasaki JPX), Initialization system for a close-coupled multiprocessor system.
  18. Eng Kai Y. (Eatontown NJ) Karol Mark J. (Fair Haven NJ) Yeh Yu S. (Freehold NJ), Interconnect fabric providing connectivity between an input and arbitrary output(s) of a group of outlets.
  19. Muramatsu Akira (Kawasaki JPX) Yoshihara Ikuo (Tama JPX) Nakao Kazuo (Sagamihara JPX) Hayashi Takehisa (Kodaira JPX) Tanaka Teruo (Hachioji JPX) Nagashima Shigeo (Hachioji JPX), Interconnection network and crossbar switch for the same.
  20. Sheinbein Daniel (Elizabeth NJ), Interoffice callback arrangement.
  21. Atac Robert (Aurora IL) Fischler Mark S. (Warrenville IL) Husby Donald E. (DeKalb IL), Interprocessor bus switching system for simultaneous communication in plural bus parallel processing system.
  22. Barner Robert P. (Rockville MD) Gulick Anne M. (Carmel NY) deVeer John A. (Millbrook NY) Oblonsky Jan G. (Brookeville MD), Loop configured data transmission system.
  23. Grondalski Robert S. (Maynard MA), Mechanism for broadcasting data in a massively parallell array processing system.
  24. Boccon-Gibod Philippe (Eybens FRX), Method and a device for booting a computer at a programmed time.
  25. Bruck Jehoshua (Palo Alto CA) Cypher Robert E. (Los Gatos CA) Ho Ching-Tien (San Jose CA), Method and apparatus for a fault-tolerant mesh with spare nodes.
  26. Miller David A. (Houston TX) Jansen Kenneth A. (Spring TX) Culley Paul R. (Cypress TX) Taylor Mark (Houston TX) Izquierdo Javier F. (Houston TX), Method and apparatus for independently resetting processors and cache controllers in multiple processor systems.
  27. Munter Ernst A. (Kanata CAX) Perryman Ian (Ottawa CAX), Method and apparatus for input-buffered asynchronous transfer mode switching.
  28. Konishi Kuniyoshi (Tokyo JPX), Method and apparatus for managing address information utilized in message transmission and reception.
  29. Miller David A. (Houston TX) Jansen Kenneth A. (Spring TX) McGraw Montgomery C. (Spring TX) Cepulis Darren J. (Houston TX), Method and apparatus for resetting multiple processors using a common ROM.
  30. Cepulis Darren J. (Houston TX) Gagliardi Louis R. (Tomball TX), Method of booting a multiprocessor computer where execution is transferring from a first processor to a second processor.
  31. Perlman Radia (Acton MA), Method of multicast message distribution.
  32. Baum Richard I. (Poughkeepsie NY) Brotman Charles H. (Poughkeepsie NY) Rymarczyk James W. (Poughkeepsie NY), Multiprocessing packet switching connection system having provision for error correction and recovery.
  33. Allen James C. (San Jose CA) Bartlett Wendy B. (Los Altos CA) Johnson ; III Hoke S. (San Jose CA) Fisher Steven D. (San Mateo CA) Larson Richard O. (Fremont CA) Peck John C. (Mountain View CA), Multiprocessor multisystem communications network.
  34. Allen James C. (San Jose CA) Bartlett Wendy B. (Los Altos CA) Johnson Hoke S. (San Jose CA) Fisher Steven D. (Belmont MA) Larson Richard O. (Fremont CA) Peck John C. (Mountain View CA), Multiprocessor multisystem communications network.
  35. Jewett Douglas E. (Austin TX), Multiprocessor system with each processor executing the same instruction sequence and hierarchical memory providing on d.
  36. Goto Takeshi (Shijonawate JPX), Multistation display system for controlling a display monitor associated with plural audio video devices.
  37. Dighe Rajiv S. (Middletown NJ) May ; Jr. Carl J. (Holmdel NJ), Packet cross connect switch system including improved throughput.
  38. McMillen Robert J. (2508 E. Willow #104 Long Beach CA 90806), Packet switched multiple queue NXM switch node and processing method.
  39. McMillen Robert J. (Long Beach CA) Rosman Andrew (Los Alamitos CA), Packet switched multiport memory NXM switch node and processing method.
  40. Teraslinna Kari T. (Naperville IL) Toy Wing N. (Glen Ellyn IL), Packet switching network for multiple packet types.
  41. Gifford David K. (Cambridge MA), Parallel processing system with processor array having SIMD/MIMD instruction processing.
  42. Nakagoshi Junji (Tokyo JPX) Hamanaka Naoki (Tokyo JPX) Chiba Hiroyuki (Koyasu JPX) Higuchi Tatsuo (Fuchu JPX) Shutoh Shinichi (Kokubunji JPX) Ogata Yasuhiro (Akishima JPX) Takeuchi Shigeo (Hannou JPX, Parallel processor system having computing clusters and auxiliary clusters connected with network of partial networks an.
  43. Hillis W. Daniel (111 Ivy St. Brookline MA 02146) Knight ; Jr. Thomas F. (58 Douglas Rd. Belmont MA 02178) Bawden Alan (93 Jackson St. Cambridge MA 02140) Kahle Brewster L. (59 Munroe St. Somerville , Parallel processor/memory circuit.
  44. Evans Richard A. (Malvern GB2), Processing cell for fault tolerant arrays.
  45. Sakata Hironobu (Tokyo JPX), Re-synchronization system using common memory bus to transfer restart data from non-faulty processor to failed processor.
  46. McMillen, Robert J.; Watson, M. Cameron; Chura, David J., Reconfigurable, fault tolerant, multistage interconnect network and protocol.
  47. Flaherty James E. (Hudson MA) Abrahams Alan (Framingham MA), Remote bootstrapping a node over communication link by initially requesting remote storage access program which emulates.
  48. Ho Jen-Lie (Naperville IL), Resource allocation in distributed control systems.
  49. Nickolls John R. (Los Altos CA) Zapisek John (Cupertino CA) Kim Won S. (Fremont CA) Kalb Jeffery C. (Saratoga CA) Blank W. Thomas (Palo Alto CA) Wegbreit Eliot (Palo Alto CA) Van Horn Kevin (Mountain, Scalable processor to processor and processor-to-I/O interconnection network and method for parallel processing arrays.
  50. Newman Peter (750 N. Shoreline Blvd. ; Apt. 69 Mountain View CA 94043), Self-routing switching element and fast packet switch.
  51. Comroe Richard A. (East Dundee IL) Borras Jaime A. (Hialeah FL) Browand Wayne H. (Sunrise FL) Ramos Ozzie F. (Sunrise FL) Kozlowski Ted A. (Chicago IL) Mitchell Timothy A. (Plantation FL) Ekl Randy L, Serial link communications protocol.
  52. Stiffler Jack J. (Hopkinton MA) Nolan James M. (Holliston MA) Mark Peter (Boston MA) Harvey David (Brookline MA), Shared computer resource allocation system having apparatus for informing a requesting computer of the identity and busy.
  53. Balmer Keith (6 Salcombe Close Bedford (Bedfordshire) GB2 MK40 38A) Ing-Simmons Nicholas K. (74 Lincroft ; Oakley Bedford (Bedfordshire) TX GB2 MK43 7SS) Guttag Karl M. (4015 S. Sandy Ct. Missouri Ci, Switch matrix having integrated crosspoint logic and method of operation.
  54. Hamanaka Naoki (Tokyo JPX) Tanaka Teruo (Hachioji JPX) Omoda Koichiro (Sagamihara JPX) Nagashima Shigeo (Hachioji JPX), System for converting job/process identifiers into processor/process identifiers in transferring data between processes.
  55. Schomberg Hermann (Hamburg DEX), System for parallel computation with three phase processing in processor tiers in which new instructions trigger executi.
  56. Hillis W. Daniel (Cambridge MA), System for partitioning a massively parallel computer.
  57. Masuda Hiroki (Yokohama JPX) Igi Yoso (Yokohama JPX) Eto Koji (Tokyo JPX), System for switching between processors in a multiprocessor system.
  58. Bar Alfredo (Pavia ITX), Terminal board and relays casing assembly in motor compressors for refrigerators.

이 특허를 인용한 특허 (40)

  1. Whinnett, Nicholas William; Somerville, Fiona Clare Angharad, Accessing a base station.
  2. Farber, David A.; Lachman, Ronald D., Accessing data in a data processing system.
  3. Archer, Charles J.; Faraj, Daniel A., Broadcasting a message in a parallel computer.
  4. Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D.; Smith, Brian E., Collective operation protocol selection in a parallel computer.
  5. Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D.; Smith, Brian E., Collective operation protocol selection in a parallel computer.
  6. Farber, David A.; Lachman, Ronald D., Computer file system using content-dependent file identifiers.
  7. Farber, David A.; Lachman, Ronald D., Controlling access to data in a data processing system.
  8. Deroux-Dauphin Patrice,FRX ITX 38120 ; Francois Christian,FRX ITX 01390, Deflection network.
  9. Archer, Charles J.; Carey, James E.; Sanders, Philip J.; Smith, Brian E., Developing collective operations for a parallel computer.
  10. Archer, Charles J.; Carey, James E.; Sanders, Philip J.; Smith, Brian E., Developing collective operations for a parallel computer.
  11. Archer, Charles J.; Ratterman, Joseph D., Executing a gather operation on a parallel computer.
  12. Whinnett, Nick; Somerville, Fiona, Femtocell access control.
  13. Whinnett, Nick; Somerville, Fiona; Smart, Christopher, Femtocell base station.
  14. Smart, Christopher Brian, Filter.
  15. Rose, Anthony, Filter for a distributed network.
  16. Rose, Anthony, Filter for a distributed network.
  17. Rose, Anthony, Filter for a distributed network.
  18. Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D.; Smith, Brian E., Improving efficiency of a global barrier operation in a parallel computer.
  19. Archer, Charles J.; Berg, Jeremy E.; Blocksome, Michael A.; Smith, Brian E., Line-plane broadcasting in a data communications network of a parallel computer.
  20. Olofsson, Andreas, Mesh network.
  21. Whinnett, Nicholas William, Method and device in a communication network.
  22. Whinnett, Nicholas William, Method and device in a communication network.
  23. Whinnett, Nicholas William, Method and device in a communication network.
  24. Whinnett, Nicholas William, Method and device in a communication network.
  25. Whinnett, Nick, Methods and devices for reducing interference in an uplink.
  26. Shaw, Mark; Herrell, Russ William; Berke, Stuart Allen, Multiple cell computer systems and methods.
  27. Irie Naohiko,JPX ; Hamanaka Naoki,JPX ; Shibata Masabumi,JPX, Multiprocessor system with partial broadcast capability of a cache coherent processing request.
  28. Ajima, Yuichiro; Inoue, Tomohiro; Hiramoto, Shinya, Network for interconnecting computers.
  29. Archer, Charles J.; Carey, James E.; Markland, Matthew W.; Sanders, Philip J., Optimizing collective operations.
  30. Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D.; Smith, Brian E., Performing a deterministic reduction operation in a parallel computer.
  31. Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D.; Smith, Brian E., Performing a deterministic reduction operation in a parallel computer.
  32. Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D.; Smith, Brian E., Performing a global barrier operation in a parallel computer.
  33. Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D.; Smith, Brian E., Performing a scatterv operation on a hierarchical tree network optimized for collective operations.
  34. Archer, Charles J.; Peters, Amanda E.; Smith, Brian E., Performing an all-to-all data exchange on a plurality of data buffers by performing swap operations.
  35. Archer, Charles J.; Dozsa, Gabor; Ratterman, Joseph D.; Smith, Brian E., Performing an allreduce operation using shared memory.
  36. Smart, Christopher Brian, Power control.
  37. Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D.; Smith, Brian E., Processing data communications events by awakening threads in parallel active messaging interface of a parallel computer.
  38. Claydon, Anthony Peter John; Claydon, Anne Patricia, Processor architecture with switch matrices for transferring data along buses.
  39. Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D.; Smith, Brian E., Send-side matching of data communications messages.
  40. Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D.; Smith, Brian E., Send-side matching of data communications messages.
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