이 특허를 인용한 특허 (115)

1. Kuo, Bob Shih-Wei, Blind via capture pad structure.

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2. Kuo, Bob Shih-Wei, Blind via capture pad structure fabrication method.

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3. Huemoeller, Ronald Patrick; Rusli, Sukianto; Hiner, David Jon, Buildup dielectric and metallization process and semiconductor package.

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4. Huemoeller, Ronald Patrick; Rusli, Sukianto; Hiner, David Jon, Buildup dielectric layer having metallization pattern semiconductor package fabrication method.

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5. Huemoeller, Ronald Patrick; Rusli, Sukianto; Hiner, David Jon, Buildup dielectric layer having metallization pattern semiconductor package fabrication method.

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6. Huemoeller, Ronald Patrick; Rusli, Sukianto, Circuit-on-foil process for manufacturing a laminated semiconductor package substrate having embedded conductive patterns.

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7. Huemoeller,Ronald Patrick; Rusli,Sukianto, Circuit-on-foil process for manufacturing a laminated semiconductor package substrate having embedded conductive patterns.

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8. St. Amand, Roger D., Column and stacking balls package fabrication method and structure.

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9. Darveaux, Robert Francis; Dunlap, Brett Arnold; Huemoeller, Ronald Patrick, Electronic component package fabrication method and structure.

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10. Darveaux, Robert Francis; Dunlap, Brett Arnold; Huemoeller, Ronald Patrick, Electronic component package fabrication method and structure.

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11. Huemoeller, Ronald Patrick; Rusli, Sukianto; Hiner, David Jon; Karim, Nozad Osman, Embedded metal features structure.

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12. Liu, Yi-Chun; Cheng, Wei-Ming; Chen, Tsung-Yuan; Chiang, Shu-Sheng, Embedded structure.

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13. Huemoeller, Ronald Patrick; Rusli, Sukianto; Hiner, David Jon, Encapsulated semiconductor package.

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14. Hiner, David Jon; Huemoeller, Ronald Patrick, Extended landing pad substrate package structure and method.

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15. Hiner, David Jon; Huemoeller, Ronald Patrick, Extended landing pad substrate package structure and method.

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16. Scanlan, Christopher M.; St. Amand, Roger D.; Kim, Jae Dong, Fan out build up substrate stackable package and method.

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17. Bolognia, David; Adlam, Ted; Kelly, Mike, Fingerprint sensor package and method.

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18. Manfred Elsasser DE, Flat resistance heating element.

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19. Darveaux, Robert Francis; Bancod, Ludovico E.; Mattei, Marnie Ann; Olson, Timothy Lee, Flex circuit package and method.

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20. Hiner,David Jon; Huemoeller,Ronald Patrick; Rusli,Sukianto, Integrated circuit substrate having laser-exposed terminals.

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21. Lee, DongHoon; Kim, DoHyung; Park, JungSoo; Han, SeungChul; Kim, JooHyun; Hiner, David Jon; Huemoeller, Ronald Patrick; Kelly, Michael G., Interposer, manufacturing method thereof, semiconductor package using the same, and method for fabricating the semiconductor package.

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22. Kuo, Bob Shih-Wei; Dunlap, Brett Arnold; Bolognia, David, Light emitting diode (LED) package and method.

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23. Hirose, Naohiro; Noda, Kouta; Segawa, Hiroshi; En, Honjin; Tsukada, Kiyotaka; Ishida, Naoto; Asano, Kouji; Shouda, Atsushi, Manufacturing method of a multilayered printed circuit board having an opening made by a laser, and using electroless and electrolytic plating.

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24. Dunlap, Brett Arnold; Darveaux, Robert Francis, Mechanical tape separation package.

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25. Dunlap, Brett Arnold; Darveaux, Robert Francis, Mechanical tape separation package and method.

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26. Baum, Abraham; Hoch, Elisha; Schnitzer, Israel; Kacir, Lior; Rabinovich, Felix; Reuben, Ilia, Method and apparatus for manufacturing medical support devices.

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27. Law,Kam S.; Bachrach,Robert Z.; White,John M.; Shang,Quanyuan, Method and apparatus for metallization of large area substrates.

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28. Lee,Wen Chin; Lin,Cheng Hsien, Method for forming stacked via-holes in a multilayer printed circuit board.

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29. Hiner,David Jon; Huemoeller,Ronald Patrick; Rusli,Sukianto, Method for making an integrated circuit substrate having embedded back-side access conductors and vias.

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30. Huemoeller,Ronald Patrick; Rusli,Sukitano, Method for making an integrated circuit substrate having embedded passive components.

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31. Hiner, David Jon; Huemoeller, Ronald Patrick; Rusli, Sukianto, Method for making an integrated circuit substrate having laminated laser-embedded circuit layers.

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32. Huemoeller,Ronald Patrick; Rusli,Sukianto, Method for making an integrated circuit substrate having laser-embedded conductive patterns.

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33. Liu, Yi-Chun; Cheng, Wei-Ming; Chen, Tsung-Yuan; Chiang, Shu-Sheng, Method for making embedded circuit structure.

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34. Dong Shin KR; Keon Yang Park KR; Young Hwan Shin KR; Byung Kook Sun KR; Jae Heun Joung KR, Method for manufacturing build-up multi-layer printed circuit board by using yag laser.

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35. Kariya, Takashi; Tanaka, Hironori, Method for manufacturing printed circuit board.

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36. Asai, Motoo; Hiramatsu, Yasuji, Method for manufacturing printed wiring board.

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37. Baum,Abraham; Hoch,Elisha; Schnitzer,Israel; Kacir,Lior; Rabinovich,Felix; Ilia,Reuben, Method for producing a coated medical support device.

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38. Rusli, Sukianto; Huemoeller, Ronald Patrick, Method of fabricating an embedded circuit pattern.

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39. Li, Yonggang; Salama, Islam; Gurumurthy, Charan, Method of forming a multilayer substrate core structure using sequential microvia laser drilling and substrate core structure formed according to the method.

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40. Dunlap, Brett Arnold, Method of forming a plurality of electronic component packages.

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41. Li, Yonggang; Salama, Islam; Gurumurthy, Charan; Azimi, Hamid, Method of forming a substrate core structure using microvia laser drilling and conductive layer pre-patterning and substrate core structure formed according to the method.

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42. Li, Yonggang; Salama, Islam; Gurumurthy, Charan; Azimi, Hamid, Method of forming a substrate core structure using microvia laser drilling and conductive layer pre-patterning and substrate core structure formed according to the method.

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43. Chen, Ying-Lin; Chen, Yung-Chou, Method of making a flexible printed circuit board.

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44. Carroll Keith C.,CAXITX L0N 1E0, Method of manufacturing a female electrical connector in a single layer flexible polymeric dielectric film substrate.

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45. Hirose, Naohiro; Noda, Kouta; Segawa, Hiroshi; En, Honjin; Tsukada, Kiyotaka; Ishida, Naoto; Asano, Kouji; Shouda, Atsushi, Method of manufacturing a multilayered printed circuit board.

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46. Takada, Masaru; Tsukada, Kiyotaka; Kobayashi, Hiroyuki; Minoura, Hisashi; Ukai, Yoshikazu; Kondo, Mitsuhiro, Method of manufacturing a printed wiring board having a previously formed opening hole in an innerlayer conductor circuit.

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47. Hiner,David Jon; Huemoeller,Ronald Patrick; Rusli,Sukianto, Method of manufacturing a semiconductor package.

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48. Naito, Toshiki; Shinogi, Yoshifumi; Uenda, Daisuke, Method of manufacturing double-sided circuit board.

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49. Hirose,Naohiro; Noda,Kouta; Segawa,Hiroshi; En,Honjin; Tsukada,Kiyotaka; Ishida,Naoto; Asano,Kouji; Shouda,Atsushi, Method of manufacturing multilayered circuit board.

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50. Nicholls, Louis W.; St. Amand, Roger D.; Kim, Jin Seong; Jung, Woon Kab; Yang, Sung Jin; Darveaux, Robert F., Methods and structures for increasing the allowable die size in TMV packages.

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51. Dreiza, Mahmoud; Ballantine, Andrew; Shumway, Russell Scott, Molded cavity substrate MEMS package fabrication method and structure.

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52. Huemoeller, Ronald Patrick; Hiner, David Jon; Lie, Russ, Multi-level circuit substrate fabrication method.

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53. Hirose, Naohiro; En, Honjin, Multilayer build-up wiring board.

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54. Hirose, Naohiro; En, Honjin, Multilayer build-up wiring board.

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55. Hirose, Naohiro; En, Honjin, Multilayer build-up wiring board including a chip mount region.

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56. Hirose, Naohiro; Noda, Kouta; Segawa, Hiroshi; En, Honjin; Tsukada, Kiyotaka; Ishida, Naoto; Asano, Kouji; Shouda, Atsushi, Multilayered printed circuit board and manufacturing method thereof.

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57. Wakihara, Yoshinori; Yamada, Kazuhito, Printed circuit boards and method of producing the same.

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58. Wakihara,Yoshinori; Yamada,Kazuhito, Printed circuit boards and method of producing the same.

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59. Asai, Motoo; Hiramatsu, Yasuji, Printed wiring board and method for manufacturing the same.

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60. Asai, Motoo; Hiramatsu, Yasuji; Wakihara, Yoshinori; Yamada, Kazuhito, Printed wiring board and method for manufacturing the same.

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61. Asai, Motoo; Hiramatsu, Yasuji; Wakihara, Yoshinori; Yamada, Kazuhito, Printed wiring board and method for manufacturing the same.

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62. Asai,Motoo, Printed wiring board and method for manufacturing the same.

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63. Asai,Motoo; Hiramatsu,Yasuji, Printed wiring board and method for manufacturing the same.

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64. Asai,Motoo; Hiramatsu,Yasuji, Printed wiring board and method for manufacturing the same.

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65. Wakihara, Yoshinori; Yamada, Kazuhito, Printed wiring board and method for manufacturing the same.

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66. Wakihara,Yoshinori; Yamada,Kazuhito, Printed wiring board and method for manufacturing the same.

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67. Kim, Do Hyung; Kang, Dae Byoung; Han, Seung Chul, Semiconductor device.

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68. Kim, Jin Seong; Park, Dong Joo; Kim, Kwang Ho; Ahn, Ye Sul, Semiconductor device and fabricating method thereof.

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69. Kim, Sang Won; Jung, Boo Yang; Kim, Sung Kyu; Yoo, Min; Lee, Seung Jae, Semiconductor device and fabricating method thereof.

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70. Clark, David; Zwenger, Curtis, Semiconductor device and manufacturing method thereof.

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71. Paek, Jong Sik; Do, Won Chul; Park, Doo Hyun; Park, Eun Ho; Oh, Sung Jae, Semiconductor device and manufacturing method thereof.

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72. Paek, Jong Sik; Do, Won Chul; Park, Doo Hyun; Park, Eun Ho; Oh, Sung Jae, Semiconductor device and manufacturing method thereof.

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73. Ryu, Ji Yeon; Kim, Byong Jin; Shim, Jae Beum, Semiconductor device and manufacturing method thereof.

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74. Kim, Jin Seong; Park, Dong Joo; Kim, Kwang Ho; Yoo, Hee Yeoul; Jeong, Jeong Wung, Semiconductor device having overlapped via apertures.

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75. Kim, Jin Seong; Park, Dong Joo; Kim, Kwang Ho; Yoo, Hee Yeoul; Jeong, Jeong Wung, Semiconductor device having overlapped via apertures.

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76. Kim, Jin Seong; Park, Dong Joo; Kim, Kwang Ho; Yoo, Hee Yeoul; Jeong, Jeong Wung, Semiconductor device having overlapped via apertures.

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77. Kelly, Michael; Hiner, David; Huemoeller, Ronald; St. Amand, Roger, Semiconductor package and fabricating method thereof.

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78. Kelly, Michael; Hiner, David; Huemoeller, Ronald; St. Amand, Roger, Semiconductor package and fabricating method thereof.

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79. Kelly, Michael; Hiner, David; Huemoeller, Ronald; St. Amand, Roger, Semiconductor package and fabricating method thereof.

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80. Huemoeller,Ronald Patrick; Hiner,David Jon; Rusli,Sukianto, Semiconductor package and substrate having multi-level vias.

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81. Huemoeller,Ronald Patrick; Hiner,David Jon; Rusli,Sukianto, Semiconductor package and substrate having multi-level vias fabrication method.

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82. Scanlan, Christopher Marc; Huemoeller, Ronald Patrick, Semiconductor package including a top-surface metal layer for implementing circuit features.

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83. Scanlan, Christopher Marc; Huemoeller, Ronald Patrick, Semiconductor package including a top-surface metal layer for implementing circuit features.

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84. Scanlan, Christopher Marc; Huemoeller, Ronald Patrick, Semiconductor package including a top-surface metal layer for implementing circuit features.

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85. Hiner, David Jon; Huemoeller, Ronald Patrick; Rusli, Sukianto, Semiconductor package including top-surface terminals for mounting another semiconductor package.

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86. Hiner, David Jon; Huemoeller, Ronald Patrick; Rusli, Sukianto, Semiconductor package including top-surface terminals for mounting another semiconductor package.

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87. Hiner, David Jon; Huemoeller, Ronald Patrick; Rusli, Sukianto, Semiconductor package including top-surface terminals for mounting another semiconductor package.

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88. Huemoeller,Ronald Patrick; Hiner,David Jon; Rusli,Sukianto; Sheridan,Richard, Semiconductor package substrate fabrication method.

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89. Darveaux, Robert Francis; St. Amand, Roger D.; Perelman, Vladimir, Stackable package and method.

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90. Darveaux, Robert Francis; St. Amand, Roger D.; Perelman, Vladimir, Stackable package and method.

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91. Bancod, Ludovico E.; Kim, Jin Seong; Wachtler, Kurt Peter, Stackable plasma cleaned via package and method.

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92. Yoshida, Akito; Dreiza, Mahmoud; Zwenger, Curtis Michael, Stackable protruding via package and method.

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93. Darveaux, Robert Francis; Bancod, Ludovico; Yoshida, Akito, Stackable treated via package and method.

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94. Yoshida, Akito; Dreiza, Mahmoud, Stackable variable height via package and method.

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95. Yoshida, Akito; Dreiza, Mahmoud, Stackable variable height via package and method.

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96. Yoshida, Akito; Dreiza, Mahmoud; Zwenger, Curtis Michael, Stackable via package and method.

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97. Yoshida, Akito; Dreiza, Mahmoud; Zwenger, Curtis Michael, Stackable via package and method.

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98. Yoshida, Akito; Dreiza, Mahmoud; Zwenger, Curtis Michael, Stackable via package and method.

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99. Yoshida, Akito; Dreiza, Mahmoud; Zwenger, Curtis Michael, Stackable via package and method.

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100. Yoshida, Akito; Dreiza, Mahmoud; Zwenger, Curtis Michael, Stackable via package and method.

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101. Yoshida, Akito; Dreiza, Mahmoud; Zwenger, Curtis Michael, Stackable via package and method.

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102. Kuo, Bob Shih-Wei; Dunlap, Brett Arnold; Troche, Jr., Louis B.; Syed, Ahmer; Shumway, Russell, Stacked and staggered die MEMS package and method.

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103. Longo, Joseph Marco; Scanlan, Christopher M., Stacked redistribution layer (RDL) die assembly package.

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104. Longo, Joseph Marco; Scanlan, Christopher M., Stacked redistribution layer (RDL) die assembly package.

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105. Scanlan, Christopher M., Stacked redistribution layer (RDL) die assembly package.

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106. Scanlan, Christopher M., Stacked redistribution layer (RDL) die assembly package.

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107. Huemoeller, Ronald Patrick; Rusli, Sukianto, Straight conductor blind via capture pad structure and fabrication method.

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108. Muramatsu, Shigetsugu; Imai, Kazunari, Substrate for mounting electronic parts thereon and method of manufacturing same.

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109. Huemoeller, Ronald Patrick; Rusli, Sukianto; Hiner, David Jon, Substrate having stiffener fabrication method.

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110. Tanaka, Hironori; Kawano, Shuichi, Substrate with low-elasticity layer and low-thermal-expansion layer.

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111. Dunlap, Brett Arnold; Copia, Alexander William, Thin stackable package and method.

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112. Chang, Chien-Wei, Translation pad flip chip (TPFC) method for improving micro bump pitch IC substrate structure and manufacturing process.

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113. St. Amand, Roger D., Underfill contacting stacking balls package fabrication method and structure.

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114. Yang, Chih-kuang, Via structure in multi-layer substrate.

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115. Jung, Boo Yang; Paek, Jong Sik; Lee, Choon Heung; Park, In Bae; Kim, Sang Won; Kim, Sung Kyu; Lee, Sang Gyu, Wafer level fan out semiconductor device and manufacturing method thereof.

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