이 특허를 인용한 특허 (155)

1. Wang,Bonnie I.; Huang,Joseph; Sung,Chiakang; Chong,Yan; Nguyen,Khai; Kim,Henry, Apparatus and method for controlling a delay chain.

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2. Simkins, James M.; Young, Steven P.; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y., Applications of cascading DSP slices.

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3. Ching, Alvin Y.; Wong, Jennifer; New, Bernard J.; Simkins, James M.; Thendean, John M.; Wong, Anna Wing Wah; Vadi, Vasisht Mantra, Architectural floorplan for a digital signal processing circuit.

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4. Simkins,James M.; Young,Steven P.; Wong,Jennifer; New,Bernard J.; Ching,Alvin Y., Arithmetic circuit with multiplexed addend inputs.

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5. Wong, Anna Wing Wah; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Thendean, John M.; Simkins, James M.; Vadi, Vasisht Mantra; Schultz, David P., Arithmetic logic unit circuit.

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6. Ridgeway David J., Bus structure for modularized chip with FPGA modules.

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7. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd, Bus systems and reconfiguration methods.

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8. Vorbach, Martin; Münch, Robert, Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs.

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9. Kaviani, Alireza S.; Mohan, Sundararajarao; Wittig, Ralph D.; Young, Steven P.; New, Bernard J., Configurable logic block for PLD with logic gate for combining output with another configurable logic block.

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10. Bernard J. New ; Ralph D. Wittig ; Sundararajarao Mohan, Configurable logic element with expander structures.

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11. New, Bernard J.; Wittig, Ralph D.; Mohan, Sundararajarao, Configurable logic element with expander structures.

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12. New, Bernard J.; Wittig, Ralph D.; Mohan, Sundararajarao, Configurable logic element with expander structures.

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13. New,Bernard J.; Wittig,Ralph D.; Mohan,Sundararajarao, Configurable logic element with expander structures.

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14. New,Bernard J.; Wittig,Ralph D.; Mohan,Sundararajarao, Configurable logic element with expander structures.

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15. Vorbach, Martin; Nückel, Armin, Configurable logic integrated circuit having a multidimensional structure of configurable elements.

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16. Ralph D. Wittig ; Sundararajarao Mohan ; Bernard J. New, Configurable lookup table for programmable logic devices.

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17. Chong,Yan; Sung,Chiakang; Huang,Joseph; Pan,Philip, Control circuit for self-compensating delay chain for multiple-data-rate interfaces.

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18. Vorbach, Martin; Thomas, Alexander, Data processing device and method.

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19. Vorbach, Martin; Thomas, Alexander, Data processing device and method.

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20. Vorbach, Martin; Thomas, Alexander, Data processing device and method.

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21. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing method and device.

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22. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing method and device.

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23. Vorbach, Martin; Münch, Robert, Data processor having disabled cores.

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24. Vorbach, Martin, Device including a field having function cells and information providing cells controlled by the function cells.

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25. New, Bernard J.; Vadi, Vasisht Mantra; Wong, Jennifer; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Simkins, James M., Digital signal processing block having a wide multiplexer.

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26. Simkins, James M.; Ching, Alvin Y.; Thendean, John M.; Vadi, Vasisht M.; Poon, Chi Fung; Rab, Muhammad Asim, Digital signal processing block with preadder stage.

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27. Simkins, James M.; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Vadi, Vasisht Mantra, Digital signal processing circuit having a SIMD circuit.

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28. Vadi, Vasisht Mantra; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Simkins, James M., Digital signal processing circuit having a pattern circuit for determining termination conditions.

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29. Vadi, Vasisht Mantra; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Simkins, James M., Digital signal processing circuit having a pattern detector circuit.

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30. New, Bernard J.; Wong, Jennifer; Simkins, James M.; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Vadi, Vasisht Mantra, Digital signal processing circuit having a pattern detector circuit for convergent rounding.

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31. Simkins, James M.; Thendean, John M.; Vadi, Vasisht Mantra; New, Bernard J.; Wong, Jennifer; Wong, Anna Wing Wah; Ching, Alvin Y., Digital signal processing circuit having a pre-adder circuit.

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32. Thendean, John M.; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Simkins, James M.; Wong, Anna Wing Wah; Vadi, Vasisht Mantra, Digital signal processing circuit having an adder circuit with carry-outs.

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33. Simkins, James M.; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Vadi, Vasisht Mantra, Digital signal processing circuit having input register blocks.

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34. Simkins, James M.; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Vadi, Vasisht Mantra; Schultz, David P., Digital signal processing element having an arithmetic logic unit.

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35. Snider, Gregory S.; Kuekes, Philip J., FPGA architecture at conventional and submicron scales.

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36. Snider,Gregory S.; Kuekes,Philip J., FPGA architecture at conventional and submicron scales.

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37. Wittig Ralph D. ; Mohan Sundararajarao ; Carberry Richard A., FPGA configurable logic block with multi-purpose logic/memory circuit.

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38. Wittig Ralph D. ; Mohan Sundararajarao ; Carberry Richard A., FPGA configurable logic block with multi-purpose logic/memory circuit.

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39. Wittig Ralph D. ; Mohan Sundararajarao ; Carberry Richard A., FPGA configurable logic block with multi-purpose logic/memory circuit.

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40. Agrawal Om P. ; Chang Herman M. ; Sharpe-Geisler Bradley A. ; Nguyen Bai, FPGA integrated circuit having embedded SRAM memory blocks with registered address and data input sections.

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41. Agrawal,Om P.; Chang,Herman M.; Sharpe Geisler,Bradley A.; Nguyen,Bai, FPGA integrated circuit having embedded sram memory blocks with registered address and data input sections.

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42. Liu,Tong; Lien,Jung Cheun; Feng,Sheng; Huang,Eddy C.; Sun,Chung Yuan; Liao,Naihui; Xiong,Weidong, Freeway routing system for a gate array.

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43. Vorbach, Martin; May, Frank, Hardware definition method including determining whether to implement a function as hardware or software.

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44. Kevin B. Skahill ; Haneef Mohammed, Hybrid product term and look-up table-based programmable logic device with improved speed and area efficiency.

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45. Skahill Kevin B. ; Mohammed Haneef, Hybrid product term and look-up table-based programmable logic device with improved speed and area efficiency.

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46. Skahill Kevin B. ; Mohammed Haneef, Hybrid product term and look-up table-based programmable logic device with improved speed and area efficiency.

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47. Vorbach, Martin; Münch, Robert, I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures.

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48. Vorbach, Martin; Münch, Robert, I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures.

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49. Vorbach, Martin; Munch, Robert, I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures.

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50. Vorbach, Martin; Munch, Robert, I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures.

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51. Ngai, Tony; Pedersen, Bruce; Shumarayev, Sergey; Schleicher, James; Huang, Wei-Jen; Hutton, Michael; Maruri, Victor; Patel, Rakesh; Kazarian, Peter J.; Leaver, Andrew; Mendel, David W.; Park, Jim, Interconnection and input/output resources for programmable logic integrated circuit devices.

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52. Ngai, Tony; Pedersen, Bruce; Shumarayev, Sergey; Schleicher, James; Huang, Wei-Jen; Hutton, Michael; Maruri, Victor; Patel, Rakesh; Kazarian, Peter J.; Leaver, Andrew; Mendel, David W.; Park, Jim, Interconnection and input/output resources for programmable logic integrated circuit devices.

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53. Ngai,Tony; Pedersen,Bruce; Shumarayev,Sergey; Schleicher,James; Huang,Wei Jen; Hutton,Michael; Maruri,Victor; Patel,Rakesh; Kazarian,Peter J.; Leaver,Andrew; Mendel,David W.; Park,Jim, Interconnection and input/output resources for programmable logic integrated circuit devices.

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54. Ngai,Tony; Pedersen,Bruce; Shumarayev,Sergey; Schleicher,James; Huang,Wei Jen; Hutton,Michael; Maruri,Victor; Patel,Rakesh; Kazarian,Peter J.; Leaver,Andrew; Mendel,David W.; Park,Jim, Interconnection and input/output resources for programmable logic integrated circuit devices.

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55. Ngai,Tony; Pedersen,Bruce; Shumarayev,Sergey; Schleicher,James; Huang,Wei Jen; Maruri,Victor; Patel,Rakesh, Interconnection and input/output resources for programmable logic integrated circuit devices.

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56. Tony Ngai ; Bruce Pedersen ; Sergey Shumarayev ; James Schleicher ; Wei-Jen Huang ; Michael Hutton ; Victor Maruri ; Rakesh Patel ; Peter J. Kazarian ; Andrew Leaver ; David W. Mendel ; Ji, Interconnection and input/output resources for programmable logic integrated circuit devices.

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57. Vorbach,Martin; M체nch,Robert, Internal bus system for DFPS and units with two-or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity.

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58. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.

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59. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.

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60. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.

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61. Francis B. Heile, Logic device architecture and method of operation.

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62. Heile Francis B., Logic device architecture and method of operation.

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63. Ralph D. Wittig ; Sundararajarao Mohan ; Richard A. Carberry, Logic/memory circuit having a plurality of operating modes.

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64. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logical cell array and bus system.

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65. Simkins,James M.; Young,Steven P.; Wong,Jennifer; New,Bernard J.; Ching,Alvin Y., Mathematical circuit with dynamic rounding.

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66. Wittig Ralph D. ; Mohan Sundararajarao ; Carberry Richard A., Memory array with hard and soft decoders.

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67. Lee, Andy L., Memory interface phase-shift circuitry to support multiple frequency ranges.

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68. Lee,Andy L., Memory interface phase-shift circuitry to support multiple frequency ranges.

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69. New, Bernard J.; Young, Steven P., Method and apparatus for incorporating a multiplier into an FPGA.

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70. Sun, Chung; Huang, Eddy C., Method and apparatus of memory clearing with monitoring RAM memory cells in a field programmable gated array.

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71. Sun,Chung; Huang,Eddy C., Method and apparatus of memory clearing with monitoring RAM memory cells in a field programmable gated array.

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72. Sun,Chung; Huang,Eddy C., Method and apparatus of memory clearing with monitoring RAM memory cells in a field programmable gated array.

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73. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.

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74. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.

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75. Vorbach, Martin, Method for debugging reconfigurable architectures.

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76. Vorbach, Martin, Method for debugging reconfigurable architectures.

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77. Vorbach, Martin; May, Frank; Nückel, Armin, Method for debugging reconfigurable architectures.

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78. Vorbach,Martin, Method for debugging reconfigurable architectures.

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79. Vorbach,Martin; May,Frank; N체ckel,Armin, Method for debugging reconfigurable architectures.

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80. Vorbach, Martin; Nückel, Armin, Method for interleaving a program over a plurality of cells.

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81. Vorbach, Martin; Nückel, Armin; May, Frank; Weinhardt, Markus; Cardoso, Joao Manuel Paiva, Method for processing data.

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82. Vorbach, Martin; May, Frank; Nückel, Armin, Method for the translation of programs for reconfigurable architectures.

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83. May,Frank; N？ckel,Armin; Vorbach,Martin, Method for translating programs for reconfigurable architectures.

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84. Wendling, Xavier; Simkins, James M., Method of and circuit for implementing a filter in an integrated circuit.

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85. Vorbach,Martin; M체nch,Robert, Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs, etc.).

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86. Vorbach, Martin; Munch, Robert M., Method of self-synchronization of configurable elements of a programmable module.

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87. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.

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88. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.

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89. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.

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90. Vorbach,Martin; M체nch,Robert, Method of self-synchronization of configurable elements of a programmable module.

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91. Vorbach, Martin; M?nch, Robert, Method of self-synchronization of configurable elements of a programmable unit.

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92. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.

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93. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.

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94. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.

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95. Vorbach,Martin; Baumgarte,Volker, Methods and devices for treating and processing data.

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96. Vorbach, Martin, Methods and devices for treating and/or processing data.

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97. Pan, Philip; Sung, Chiakang; Huang, Joseph; Chong, Yan; Wang, Bonnie I., Multiple data rate interface architecture.

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98. Pan, Philip; Sung, Chiakang; Huang, Joseph; Chong, Yan; Wang, Bonnie I., Multiple data rate interface architecture.

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99. Pan, Philip; Sung, Chiakang; Huang, Joseph; Chong, Yan; Wang, Bonnie I., Multiple data rate interface architecture.

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100. Pan, Philip; Sung, Chiakang; Huang, Joseph; Chong, Yan; Wang, Bonnie I., Multiple data rate interface architecture.

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101. Pan, Philip; Sung, Chiakang; Huang, Joseph; Chong, Yan; Wang, Bonnie I., Multiple data rate interface architecture.

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102. Pan, Philip; Sung, Chiakang; Huang, Joseph; Chong, Yan; Wang, Bonnie I., Multiple data rate interface architecture.

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103. Pan,Philip; Sung,Chiakang; Huang,Joseph; Chong,Yan; Wang,Bonnie I., Multiple data rate interface architecture.

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104. Vorbach, Martin, Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization.

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105. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.

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106. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.

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107. Vorbach,Martin; Baumgarte,Volker; Ehlers,Gerd; May,Frank; N체ckel,Armin, Pipeline configuration unit protocols and communication.

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108. Johnson,Brian D., Precise phase shifting using a DLL controlled, multi-stage delay chain.

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109. Vorbach,Martin; M체nch,Robert, Process for automatic dynamic reloading of data flow processors (DFPS) and units with two-or three-dimensional programmable cell architectures (FPGAS, DPGAS, and the like).

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110. Vorbach, Martin; Münch, Robert, Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like).

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111. Vorbach, Martin, Processor arrangement on a chip including data processing, memory, and interface elements.

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112. Vorbach, Martin; Münch, Robert, Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units.

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113. Vorbach, Martin; Nückel, Armin, Processor chip including a plurality of cache elements connected to a plurality of processor cores.

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114. Simkins, James M.; Young, Steven P.; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y., Programmable device with dynamic DSP architecture.

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115. Francis B. Heile, Programmable logic array device with random access memory configurable as product terms.

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116. Heile Francis B., Programmable logic array device with random access memory configurable as product terms.

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117. Heile Francis B., Programmable logic array device with random access memory configurable as product terms.

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118. Heile, Francis B., Programmable logic array device with random access memory configurable as product terms.

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119. Krishna Rangasayee, Programmable logic device incorporating function blocks operable as wide-shallow RAM.

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120. Rangasayee Krishna, Programmable logic device incorporating function blocks operable as wide-shallow RAM.

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121. Rangasayee Krishna, Programmable logic device incorporating function blocks operable as wide-shallow RAM.

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122. Simkins,James M.; Young,Steven P.; Wong,Jennifer; New,Bernard J.; Ching,Alvin Y., Programmable logic device with cascading DSP slices.

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123. Simkins,James M.; Young,Steven P.; Wong,Jennifer; New,Bernard J.; Ching,Alvin Y., Programmable logic device with pipelined DSP slices.

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124. Kaptanoglu, Sinan; Hutton, Michael D.; Schleicher, James, Programmable logic devices with bidirect ional cascades.

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125. Kobayashi Naohiro,JPX, Programmable semiconductor device providing security of circuit information.

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126. Vorbach, Martin, Reconfigurable elements.

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127. Vorbach, Martin, Reconfigurable elements.

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128. Vorbach, Martin; Baumgarte, Volker, Reconfigurable general purpose processor having time restricted configurations.

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129. John Morelli ; H. Richard Kendall, Reconfigurable logic for a computer.

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130. Vorbach,Martin; M？nch,Robert, Reconfigurable multidimensional array processor allowing runtime reconfiguration of selected individual array cells.

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131. Vorbach, Martin, Reconfigurable sequencer structure.

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132. Vorbach, Martin, Reconfigurable sequencer structure.

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133. Vorbach, Martin, Reconfigurable sequencer structure.

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134. Vorbach, Martin, Reconfigurable sequencer structure.

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135. Vorbach,Martin, Reconfigurable sequencer structure.

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136. Vorbach, Martin; Bretz, Daniel, Router.

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137. Vorbach,Martin; Bretz,Daniel, Router.

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138. Feng, Sheng; Lien, Jung-Cheun; Huang, Eddy C.; Sun, Chung-Yuan; Liu, Tong; Liao, Naihui, Routing structures for a tileable field-programmable gate array architecture.

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139. Vorbach,Martin; M？nch,Robert, Run-time reconfiguration method for programmable units.

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140. Vorbach, Martin; Münch, Robert, Runtime configurable arithmetic and logic cell.

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141. Chong,Yan; Sung,Chiakang; Wang,Bonnie I.; Huang,Joseph; Wang,Xiaobao; Pan,Philip; Chang,Tzung Chin, Self-compensating delay chain for multiple-date-rate interfaces.

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142. Lee,Andy L.; Johnson,Brian D., Soft core control of dedicated memory interface hardware in a programmable logic device.

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143. Feng, Sheng; Lien, Jung-Cheun; Huang, Eddy C.; Sun, Chung-Yuan; Liu, Tong; Liao, Naihui; Xiong, Weidong, Tileable field-programmable gate array architecture.

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144. Feng, Sheng; Lien, Jung-Cheun; Huang, Eddy C.; Sun, Chung-Yuan; Liu, Tong; Liao, Naihui; Xiong, Weidong, Tileable field-programmable gate array architecture.

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145. Feng,Sheng; Lien,Jung Cheun; Huang,Eddy C.; Sun,Chung Yuan; Liu,Tong; Liao,Naihui; Xiong,Weidong, Tileable field-programmable gate array architecture.

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146. Feng,Sheng; Lien,Jung Cheun; Huang,Eddy C.; Sun,Chung Yuan; Liu,Tong; Liao,Naihui; Xiong,Weidong, Tileable field-programmable gate array architecture.

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147. Feng,Sheng; Lien,Jung Cheun; Huang,Eddy C.; Sun,Chung Yuan; Liu,Tong; Liao,Naihui; Xiong,Weidong, Tileable field-programmable gate array architecture.

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148. Jung-Cheun Lien ; Sheng Feng ; Eddy C. Huang ; Chung-Yuan Sun ; Tong Liu ; Naihui Liao TW, Tileable field-programmable gate array architecture.

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149. Lien, Jung-Cheun; Feng, Sheng; Huang, Eddy C.; Sun, Chung-Yuan; Liu, Tong; Liao, Naihui, Tileable field-programmable gate array architecture.

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150. Lien, Jung-Cheun; Feng, Sheng; Huang, Eddy C.; Sun, Chung-Yuan; Liu, Tong; Liao, Naihui, Tileable field-programmable gate array architecture.

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151. Lien,Jung Cheun; Sun,Chung Yuan; Liu,Tong; Zhang,Zili; Feng,Sheng; Huang,Eddy C.; Liao,Naihui, Tileable field-programmable gate array architecture.

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152. Liu, Tong; Lien, Jung-Cheun; Feng, Sheng; Huang, Eddy C.; Sun, Chung-Yuan; Liao, Naihui, Tileable field-programmable gate array architecture.

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153. Bryant, Ian; Sun, Chung-Yuan; Feng, Sheng; Lien, Jung-Cheun; Chan, Stephen, User available body scan chain.

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154. Pedersen,Bruce B, Versatile RAM for a programmable logic device.

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155. Pedersen,Bruce B, Versatile RAM for programmable logic device.

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