이 특허를 인용한 특허 (67)

1. Fan, Xiaobo; Hennecke, Mark D.; Heath, Taliver Brooks, Accurate power allotment.

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2. Nakanishi, Toshiaki, Apparatus for detecting state of storage device.

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3. Chen, Liren; Taylor, Kirk Steven; Steenstra, Jack Brian, Battery power management for a mobile device.

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4. Weber, Wolf-Dietrich; Fan, Xiaobo; Barroso, Luiz Andre, Computer and data center load determination.

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5. Weber, Wolf-Dietrich; Fan, Xiaobo; Barroso, Luiz Andre, Computer and data center load determination.

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6. Weber, Wolf-Dietrich; Fan, Xiaobo; Barroso, Luiz Andre, Computer and data center load determination.

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7. Weber, Wolf-Dietrich; Fan, Xiaobo; Barroso, Luiz Andre, Data center load monitoring for utilizing an access power amount based on a projected peak power usage and a monitored power usage.

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8. Yagisawa, Ikuya; Matsunami, Naoto; Mannen, Akihiro; Takamoto, Kenichi, Disk array optimizing the drive operation time.

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9. Yagisawa,Ikuya; Matsunami,Naoto; Mannen,Akihiro; Takamoto,Kenichi, Disk array optimizing the drive operation time.

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10. Hakamata, Kazuo; Takamoto, Kenichi; Kobayashi, Masaaki, Disk array unit.

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11. Hakamata, Kazuo; Takamoto, Kenichi; Kobayashi, Masaaki, Disk array unit.

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12. Hakamata, Kazuo; Takamoto, Kenichi; Kobayashi, Masaaki, Disk array unit.

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13. Hakamata, Kazuo; Takamoto, Kenichi; Kobayashi, Masaaki, Disk array unit.

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14. Hakamata,Kazuo; Takamoto,Kenichi; Kobayashi,Masaaki, Disk array unit.

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15. Ofek, Eran, Dynamic power converter and method thereof.

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16. Fuchikami, Ryuji; Ishikawa, Toshihiro; Nishitoba, Takashi; Sasaki, Takayuki, Electronic apparatus and peak power-controlling method related thereto.

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17. Cain, Bradley, Expediting an operation in a computer system.

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18. Benayoun, Alain; Le Pennec, Jean-Francois; Michel, Patrick; Pin, Claude, Hardware device for processing the tasks of an algorithm in parallel.

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19. Benayoun, Alain; Le Pennec, Jean-Francois; Michel, Patrick; Pin, Claude, Hardware device for processing the tasks of an algorithm in parallel.

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20. Benayoun, Alain; Le Pennec, Jean-Francois; Michel, Patrick; Pin, Claude, Hardware device for processing the tasks of an algorithm in parallel.

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21. Matsubayashi Kazuhiro,JPX, Image processing method and apparatus and storing medium.

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22. Sano, Yoshiyuki, Information processing apparatus, computer readable medium storing program, and information processing method.

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23. Nagasaki, Katsuhiko, Information processing apparatus, control method therefor, and computer-readable memory.

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24. Togawa, Yoshifusa, Information processing apparatus, power control method and recording medium to control a plurality of driving units according to the type of data to be processed.

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25. Weber, Wolf-Dietrich; Fan, Xiaobo; Barroso, Luiz Andre, Load control in a data center.

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26. Weber, Wolf-Dietrich; Fan, Xiaobo; Barroso, Luiz Andre, Load control in a data center.

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27. Kondo,Yukio, Machine tool control apparatus.

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28. Kaushik,Shivnandan D.; Horigan,John W.; Naveh,Alon; Crossland,James B., Mechanism for processor power state aware distribution of lowest priority interrupt.

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29. Kaushik, Shivnandan D.; Horigan, John W.; Naveh, Alon; Crossland, James B., Mechanism for processor power state aware distribution of lowest priority interrupts.

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30. Hampel, Craig E.; Perego, Richard E.; Sidiropoulos, Stefanos; Tsern, Ely K.; Ware, Frederick A., Memory component with pattern register circuitry to provide data patterns for calibration.

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31. Hampel, Craig E.; Perego, Richard E.; Sidiropoulos, Stefanos; Tsern, Ely K.; Ware, Frederick A., Memory component with pattern register circuitry to provide data patterns for calibration.

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32. Hampel, Craig E.; Perego, Richard E.; Sidiropoulos, Stefanos; Tsern, Ely K.; Ware, Frederick A., Memory component with pattern register circuitry to provide data patterns for calibration.

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33. Hampel, Craig E.; Perego, Richard E.; Sidiropoulos, Stefanos; Tsern, Ely K.; Ware, Frederick A., Memory component with pattern register circuitry to provide data patterns for calibration.

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34. Hampel, Craig E.; Perego, Richard E.; Sidiropoulos, Stefanos; Tsern, Ely K.; Ware, Frederick A., Memory component with pattern register circuitry to provide data patterns for calibration.

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35. Hampel,Craig E.; Perego,Richard E.; Sidiropoulos,Stefanos S.; Tsern,Ely K.; Ware,Fredrick A., Memory device signaling system and method with independent timing calibration for parallel signal paths.

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36. Ofek, Eran, Method and apparatus for optimizing self-power consumption of a controller-based device.

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37. Fan, Xiaobo; Hennecke, Mark D.; Heath, Taliver Brooks, Method of correlating power in a data center by fitting a function to a plurality of pairs of actual power draw values and estimated power draw values determined from monitored CPU utilization of a statistical sample of computers in the data center.

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38. Inoue, Keisuke, Methods and apparatus for achieving thermal management using processing task scheduling.

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39. Inoue, Keisuke, Methods and apparatus for achieving thermal management using processing task scheduling.

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40. Inoue, Keisuke, Methods and apparatus for achieving thermal management using processing task scheduling.

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41. Inoue,Keisuke, Methods and apparatus for achieving thermal management using processor manipulation.

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42. Rhee, Ann; Chatterjee, Sumanta; Loaiza, Juan, Methods for automatic group switching according to a resource plan.

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43. Rhee,Ann; Chatterjee,Sumanta; Loaiza,Juan, Methods for selectively quiescing a computer system.

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44. Taishi Nogami JP, Multi-tasking system, recording medium in which program thereof is recorded, and processing device.

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45. Liu,Yonghe, Optimal power saving scheduler for 802.11e APSD.

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46. Hampel, Craig E.; Perego, Richard E.; Sidiropoulos, Stefanos S.; Tsern, Ely K.; Ware, Fredrick A., Phase adjustment apparatus and method for a memory device signaling system.

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47. Hampel, Craig E.; Perego, Richard E.; Sidiropoulos, Stefanos S.; Tsern, Ely K.; Ware, Fredrick A., Phase adjustment apparatus and method for a memory device signaling system.

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48. Suzuoki, Masakazu; Yamazaki, Takeshi, Power management for processing modules.

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49. Kawanishi,Toshiharu; Izuta,Naoki; Kajiyashiki,Satoshi; Matsumori,Hitoshi; Semii,Masato; Harada,Minoru, Power supply control device, apparatus equipped therewith and recording medium.

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50. Dave Bharat P. ; Jha Niraj K., Power-related hardware-software co-synthesis of heterogeneous distributed embedded systems.

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51. Weber, Wolf-Dietrich; Fan, Xiaobo; Barroso, Luiz Andre, Powering a data center.

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52. Kusu, Tomomichi; Hosoda, Ikuo, Redundant amplifier and switching method thereof.

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53. Ofek, Eran, Self-resonance sensing dynamic power converter and method thereof.

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54. Kawakita, Daisuke; Hori, Toshikazu, Semiconductor device and processor system including the same.

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55. Intrater, Gideon David, Software controlled power limiting in USB to SATA bridge.

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56. Kakeda, Tomoaki; Kusama, Takato; Beniyama, Nobuo, Storage management system, storage hierarchy management method, and management server capable of rearranging storage units at appropriate time.

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57. Talkin, David; Brooks, Alec, Supplying grid ancillary services using controllable loads.

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58. Browne, Michael E.; Dow, Eli M.; Laser, Marie R.; Yu, Jessie, Suspend profiles and hinted suspending.

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59. Fenger, Russell J.; Puthiyedath, Leena K., System and method to optimize OS scheduling decisions for power savings based on temporal characteristics of the scheduled entity and system workload.

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60. Rhee,Ann; Chatterjee,Sumanta; Loaiza,Juan, System for allocating resource using the weight that represents a limitation on number of allowance active sessions associated with each resource consumer group.

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61. Rhee,Ann; Chatterjee,Sumanta; Loaiza,Juan, System for computing an estimate execution time by totaling the time value base on an architecture or a software operating environment.

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62. Chauvel,Gerard; D'Inverno,Dominique; Edwards,Darvin R., Temperature field controlled scheduling for processing systems.

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63. Borutta Richard ; Burack John J. ; Occhipinti Michael V. ; Manock John C., Testing attachment reliability of devices.

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64. Hampel, Craig E.; Perego, Richard E.; Sidiropoulos, Stefanos S.; Tsern, Ely K.; Ware, Fredrick A., Timing calibration apparatus and method for a memory device signaling system.

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65. Miyazaki, Keiji, Transmission device and method for putting transmission device to sleep.

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66. Maruyama, Kazuna; Mito, Koji; Shibamiya, Yoshikazu; Urabe, Hirofumi; Matsubayashi, Kazuhiro; Shikata, Yasushi, Web information processing apparatus and web information processing method.

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67. Mito, Koji; Matsubayashi, Kazuhiro; Maruyama, Kazuna; Urabe, Hirofumi, Web information processing apparatus and web information processing method, and information processing apparatus and information processing apparatus control method.

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