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Electronic device and semiconductor package 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
  • H01L-023/52
  • H01L-029/40
출원번호 US-0982417 (1997-12-02)
우선권정보 JP-0323169 (1996-12-03)
발명자 / 주소
  • Iwasaki Ken,JPX
출원인 / 주소
  • Kabushiki Kaisha Toshiba, JPX
대리인 / 주소
    Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
인용정보 피인용 횟수 : 98  인용 특허 : 4

초록

The electronic device has a structure that a semiconductor package (10) is mounted on a motherboard (21), and a buffer layer (41) for relieving a stress, which is produced due to a difference of physical properties between the semiconductor package (10) and the motherboard (21), is mounted on the el

대표청구항

[ What is claimed is:] [1.] An electronic device, comprising:a first wiring substrate having a first face, the first face of the first wiring substrate having a first region and a second region, connecting terminals formed on the first region, and the first wiring substrate having a first thermal ex

이 특허에 인용된 특허 (4)

  1. Tomura Yoshihiro (Hirakata JPX) Bessho Yoshihiro (Higashiosaka JPX) Hakotani Yasuhiko (Nishinomiya JPX), Chip package, a chip carrier, a terminal electrode for a circuit substrate and a chip package-mounted complex.
  2. Degani Yinon (Highland Park NJ) Dudderar Thomas D. (Chatham NJ) Han Byung J. (Scotch Plains NJ) Raju Venkataram R. (New Providence NJ), Electronic device package having electronic device boonded, at a localized region thereof, to circuit board.
  3. Jimarez Miguel Angel ; Sarkhel Amit Kumar ; White Lawrence Harold, Solder hierarchy for chip attachment to substrates.
  4. Suyama Takayuki,JPX ; Hasegawa Shinichi,JPX, Tape carrier for increasing the number of terminals between the tape carrier and a substrate.

이 특허를 인용한 특허 (98)

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  9. Corisis,David J., Chip scale package with heat spreader.
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  14. Alcoe, David J., Compliant laminate connector.
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  18. Murali Venkatesan ; Vodrahalli Nagesh ; Kaiser Brian A., Dielectric decal for a substrate of an integrated circuit package.
  19. Lee,Teck Kheng; Lee,Kian Chai; Khoo,Sian Yong, Double bumping of flexible substrate for first and second level interconnects.
  20. Pei Wen-Chun,TWX, Electrical socket.
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  22. Soga,Tasao; Shimokawa,Hanae; Nakatsuka,Tetsuya; Miura,Kazuma; Negishi,Mikio; Nakajima,Hirokazu; Endoh,Tsuneo, Electronic device.
  23. Lee, Teck Kheng, Elimination of RDL using tape base flip chip on flex for die stacking.
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  29. Saitoh Tohru,JPX, Flip chip bonding land waving prevention pattern.
  30. Lee, Teck Kheng, Flip chip packaging using recessed interposer terminals.
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  32. Weissbach, Ernst-A.; Ertl, Juergen, Flip-chip module and method for the production thereof.
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  35. Schwiebert Matthew K. ; Hutchison Brian R. ; Chew Geary L. ; Barnett Ron, High-frequency electronic package with arbitrarily-shaped interconnects and integral shielding.
  36. Cook, William Paul; DeFosse, Stephen Francis; Droege, Curtis Ray; Gogate, Hrishikesh Pramod; Hall, Eric Spencer, Ink jet semiconductor chip structure.
  37. Goida, Thomas M.; Xue, Xiaojie, Integrated device die and package with stress reduction features.
  38. Casey William J. ; Heidelberg Andrew J. ; Skinner Daniel C., Interconnect device and method for mating dissimilar electronic package footprints.
  39. Lee,Teck Kheng, Interposer configured to reduce the profiles of semiconductor device assemblies and packages including the same and methods.
  40. Alagaratnam, Maniam; Desai, Kishor V.; Patel, Sunil A., Interposer for semiconductor package assembly.
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  42. Lee,Teck Kheng, Interposer substrate and wafer scale interposer substrate member for use with flip-chip configured semiconductor dice.
  43. Kawai,Shinya; Kokubu,Masanari; Furukubo,Youji, Laminated wiring board and its mounting structure.
  44. Fang,Ming; Dubin,Valery; Lu,Daoqiang, Large bumps for optical flip chips.
  45. Sakamoto Akira,JPX, Layered printed-circuit-board and module using the same.
  46. Chung, Kilyoan; Kim, Il Ku, Light emitting diode module for lighting.
  47. Strandberg Jan I. ; Chazan David J. ; Skinner Michael P., Low-impedance high-density deposited-on-laminate structures having reduced stress.
  48. Liao, Tsung Jen, Manufacturing method for micro bump structure.
  49. Katchmar Roman,CAX, Mechanically-stabilized area-array device package.
  50. Katchmar, Roman, Mechanically-stabilized area-array device package.
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  52. Wensel Richard ; Gooch Scott, Method and apparatus for reducing BGA warpage caused by encapsulation.
  53. Szu Ming-Lun,TWX, Method for adjusting differential thermal expansion between an electrical socket and a circuit board.
  54. Akram,Salman; Farnworth,Warren M.; Wood,Alan G., Method for fabricating semiconductor components by forming conductive members using solder.
  55. Nomiya, Masato; Sakai, Norio; Nishide, Mitsuyoshi, Method for manufacturing multilayer ceramic electronic device.
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  57. Lee, Teck Kheng, Methods for assembly and packaging of flip chip configured dice with interposer.
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  60. Lee, Teck Kheng; Tan, Cher Khng Victor, Methods of forming semiconductor assemblies.
  61. Grigg,Ford B., Microelectronic devices and methods for mounting microelectronic packages to circuit boards.
  62. Hutto, Kevin W., Microelectronic workpieces and methods for manufacturing microelectronic devices using such workpieces.
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  68. Honda, Hirokazu, Multilayer interconnection board, semiconductor device having the same, and method of forming the same as well as method of mounting the semicondutor chip on the interconnection board.
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  79. Murayama Kei,JPX, Semiconductor device having a chip mounted on a rectangular substrate.
  80. Shiozawa,Masakuni; Aoyagi,Akiyoshi, Semiconductor device, electronic device, electronic apparatus, and method of manufacturing semiconductor device.
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  82. Miyasaka,Hideo, Semiconductor device, its manufacturing method, circuit board, and electronic unit.
  83. Aoyagi,Akiyoshi, Semiconductor device, semiconductor package, electronic device, electronic apparatus, and manufacturing methods of semiconductor device and electronic device.
  84. Lee,Teck Kheng; Tan,Cher Khng Victor, Semiconductor die packages with recessed interconnecting structures.
  85. Lee,Teck Kheng; Tan,Cher Khng Victor, Semiconductor die packages with recessed interconnecting structures and methods for assembling the same.
  86. Akram, Salman; Farnworth, Warren M.; Wood, Alan G., Semiconductor package having interconnect with conductive members.
  87. Takahashi Nobuaki,JPX ; Kyougoku Yoshitaka,JPX ; Hashimoto Katsumasa,JPX ; Miyazaki Shinichi,JPX, Shock resistant semiconductor device and method for producing same.
  88. Takahashi Nobuaki,JPX ; Kyougoku Yoshitaka,JPX ; Hashimoto Katsumasa,JPX ; Miyazaki Shinichi,JPX, Shock-resistant semiconductor device and method for producing same.
  89. Pei Wen-Chun,TWX, Socket connector.
  90. Ma,Hao Yun, Socket connector for carrying integrated circuit package.
  91. Blackshear, Edmund David; Cipolla, Thomas Mario; Coteus, Paul William, Stress accommodation in electronic device interconnect technology for millimeter contact locations.
  92. Thurgood, Blaine J., Stress balanced semiconductor packages, method of fabrication and modified mold segment.
  93. Yee, Abraham F.; Chipalkatti, Jayprakash; Kalchuri, Shantanu, Thermal performance of logic chip in a package-on-package structure.
  94. Jayaraman,Saikumar, Underfill and mold compounds including siloxane-based aromatic diamines.
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  98. Kamath Sundar ; Chazan David ; Beilin Solomon I., Wiring substrate with thermal insert.
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