초록 ▼

The source line is formed of a conductive layer identical to that of the word line. The individual data lines of the complementary data line are formed of an identical conductive layer which is different from that of the word line and the source line. The identical conductive layer between the word

The source line is formed of a conductive layer identical to that of the word line. The individual data lines of the complementary data line are formed of an identical conductive layer which is different from that of the word line and the source line. The identical conductive layer between the word line and source line and the complementary data line is formed with two word lines: a main word line extended in the first direction identical to that of the word line and source line and used by adopting the divided word line system: and a sub-word line used by adopting the double word line system.

대표청구항 ▼

[ What is claimed is:] [1.] A semiconductor memory device comprising:a semiconductor substrate having a main surface;a first semiconductor region formed, at a first region on said main surface, in said semiconductor substrate;a static random access memory including memory cells formed at a second re

[ What is claimed is:] [1.] A semiconductor memory device comprising:a semiconductor substrate having a main surface;a first semiconductor region formed, at a first region on said main surface, in said semiconductor substrate;a static random access memory including memory cells formed at a second region on said main surface, each of said memory cells including a first and a second inverter circuit cross-coupled with one another, said first inverter circuit including a first driver MISFET and a first load MISFET coupled in series, said second inverter circuit including a second driver MISFET and a second load MISFET coupled in series;a first insulating film formed over said driver MISFETs and said first semiconductor region so as to cover said first and said second region, wherein said load MISFETs are formed over said first insulating film;a first wiring line, formed over said first insulating film and coupled to source regions of said load MISFETs of said memory cells, for supplying a first voltage to said memory cells;a second insulating film formed over said load MISFETs and said first insulating film so as to cover said first and said second region; anda second wiring line, formed over said second insulating film, for supplying said first voltage to said first wiring line, wherein resistance of said second wiring line is lower than resistance of said first wiring line,wherein said first wiring line extends over said first and said second region and is electrically connected to said first semiconductor region through a first opening which is formed in said first insulating film,wherein said second wiring line is formed over said first region and is electrically connected to said first semiconductor region through a second opening which is formed in both said first insulating film and said second insulating film; andwherein said first opening and said second opening are positioned separately from each other within said first region such that said first semiconductor region serves to connect the first wiring line and the second wiring line to one another between the first and second openings so that said second wiring line can supply the first voltage to the first wiring line.