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특허 상세정보

Microprocessor with dynamically extendable pipeline stages and a classifying circuit

국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) G06F-009/22   
미국특허분류(USC) 395/559 ; 395/395
출원번호 US-0421434 (1995-04-12)
발명자 / 주소
출원인 / 주소
대리인 / 주소
    Conley, Rose & Tayon, PCKivlin
인용정보 피인용 횟수 : 56  인용 특허 : 13
초록

A pipelined microprocessor containing a classifying circuit is provided. The classifying circuit allows an associated pipeline stage to implement a function requiring a larger number of cascaded logic levels than the clock cycle of the microprocessor will allow. The classifying circuit is especially useful with a pipeline stage which implements a "fundamental limit" function (i.e. a function that does not naturally divide into component functions which could be implemented as separate pipeline stages). When an evaluation time larger than a clock cycle is...

대표
청구항

[ What is claimed is:] [1.] A microprocessor comprising:a clock input line wherein said clock input line is configured to convey a signal defining a clock cycle;a plurality of pipeline stages including an execute stage, said execute stage having a first functional circuit adapted to receive an input value wherein said first functional circuit is configured to operate on said input value, and wherein said first functional circuit includes cascaded levels of logic requiring a first time to evaluate instructions of a first group and requiring a second time ...

이 특허에 인용된 특허 (13)

  1. Wilhelm Neil C. (Menlo Park CA) Leonard Judson S. (Waban MA). Apparatus and method for a pipelined central processing unit in a data processing system. USP1991024991078.
  2. Wolf Gerhard (Munich DT). Associative memory having separately associable zones. USP1977084044338.
  3. Fry Richard E. (Round Rock TX) Hicks Troy N. (Austin TX). Data processing system with multiple execution units capable of executing instructions out of sequence. USP1994115363495.
  4. Gaither Blaine D. (Sierra Madre CA) Farley ; IV William W. (Pasadena CA) Johnson Albert (Altadena CA) Parker Brian L. (Pasadena CA). Extended address generating apparatus and method. USP1984064453212.
  5. Torng Hwa C. (Ithaca NY). Instruction issuing mechanism for processors with multiple functional units. USP1989024807115.
  6. Sharangpani Harshvardhan P. (Santa Clara CA). Method and apparatus for generating a status word in a pipelined processor. USP1996125590359.
  7. Favor John G. (San Jose CA) Van Dyke Korbin (Fremont CA) Stiles David R. (Sunnyvale CA). Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency. USP1993075226130.
  8. Zmyslowski Allan J. (Sunnyvale CA) Maier Robert M. (San Jose CA). Microprogrammable pipeline interlocks based on the validity of pipeline states. USP1989084855947.
  9. Kuriyama Kazunori (Kokubunji JPX) Shintani Yooichi (Kokubunji JPX) Yamaoka Akira (Hachioji JPX) Shonai Tohru (Kokubunji JPX) Kamada Eiki (Hachioji JPX) Inoue Kiyoshi (Tokyo JPX). Pipelined data processor capable of decoding and executing plural instructions in parallel. USP1989084858105.
  10. McFarland Harold L. (San Jose CA) Stiles David R. (Sunnyvale CA) Van Dyke Korbin S. (Fremont CA) Mehta Shrenik (San Jose CA) Favor John G. (San Jose CA) Greenley Dale R. (San Jose CA) Cargnoni Robert. Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tag. USP1993075226126.
  11. Kromer Stephen C. (Austin TX). Self configuring speed path in a microprocessor with multiple clock option. USP1997045625806.
  12. Dean Mark E. (Austin TX). Self-time processor with dynamic clock generator having plurality of tracking elements for outputting sequencing signals. USP1996095553276.
  13. Staplin Deborah K. (Chelmsford MA) Shen Jian-Kuo (Belmont MA). State controlled instruction logic management apparatus included in a pipelined processing unit. USP1992095150468.

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  8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James. Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2013098543794.
  9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James. Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements. USP2013018356161.
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