초록 ▼

A pipelined microprocessor containing a classifying circuit is provided. The classifying circuit allows an associated pipeline stage to implement a function requiring a larger number of cascaded logic levels than the clock cycle of the microprocessor will allow. The classifying circuit is especially

A pipelined microprocessor containing a classifying circuit is provided. The classifying circuit allows an associated pipeline stage to implement a function requiring a larger number of cascaded logic levels than the clock cycle of the microprocessor will allow. The classifying circuit is especially useful with a pipeline stage which implements a "fundamental limit" function (i.e. a function that does not naturally divide into component functions which could be implemented as separate pipeline stages). When an evaluation time larger than a clock cycle is required, the classifying circuit holds the associated pipeline register, thus allowing the circuit to continue uninterrupted with its evaluation. The time interval available for the fundamental limit stage is dynamically extended. Furthermore, in cycles where the fundamental limit function is not required to evaluate, the pipeline operates at a significantly higher clock rate.

대표청구항 ▼

[ What is claimed is:] [1.] A microprocessor comprising:a clock input line wherein said clock input line is configured to convey a signal defining a clock cycle;a plurality of pipeline stages including an execute stage, said execute stage having a first functional circuit adapted to receive an input

[ What is claimed is:] [1.] A microprocessor comprising:a clock input line wherein said clock input line is configured to convey a signal defining a clock cycle;a plurality of pipeline stages including an execute stage, said execute stage having a first functional circuit adapted to receive an input value wherein said first functional circuit is configured to operate on said input value, and wherein said first functional circuit includes cascaded levels of logic requiring a first time to evaluate instructions of a first group and requiring a second time to evaluate instructions of a second group, said first time being larger than said clock cycle and said second time being smaller than said clock cycle, and wherein said first functional circuit further includes an output line configured to convey an output signal; anda classifying circuit adapted to receive said input value of said first functional circuit wherein said classifying circuit is configured to generate an operation status, and wherein said operation status provides information indicative of the validity of said output signal for the current clock cycle.