초록 ▼

A flash memory device having a page buffer circuit with special testing modes. The page buffer circuit comprises a plane A and a plane B, each comprising a static random access memory array. The page buffer circuit further comprises a mode control circuit that maps the plane A and the plane B as a c

A flash memory device having a page buffer circuit with special testing modes. The page buffer circuit comprises a plane A and a plane B, each comprising a static random access memory array. The page buffer circuit further comprises a mode control circuit that maps the plane A and the plane B as a contiguous extended memory space accessible over a host bus. The page buffer circuit also maps the plane A and the plane B as a control store for a flash array controller of the flash memory device.

대표청구항 ▼

[ What is claimed is:] [3.] A computer system comprising:central processing means transferring a test command over a host bus;flash memory device receiving the test command over the host bus and extending memory space mapped to an internal page buffer resource for access according to the test comman

[ What is claimed is:] [3.] A computer system comprising:central processing means transferring a test command over a host bus;flash memory device receiving the test command over the host bus and extending memory space mapped to an internal page buffer resource for access according to the test command.