$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Apparatus and method for interfacing a peripheral device having a ROM BIOS to a PCI bus 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-012/04
  • G06F-013/40
출원번호 US-0762225 (1996-12-09)
발명자 / 주소
  • Keene David
  • Hashemi Vahid R.
출원인 / 주소
  • Cirrus Logic, Inc.
대리인 / 주소
    Lowe, Price, LeBlanc, & BeckerBell
인용정보 피인용 횟수 : 19  인용 특허 : 33

초록

An apparatus and method for providing a conversion technique to allow an eight bit ROM BIOS to be read on a 32 bit PCI bus. A separate address port for the ROM BIOS is provided which is not connected to the PCI bus. The conversion bus takes data from the ROM BIOS at a separate data port, assembles f

대표청구항

[ We claim:] [1.] A computer peripheral device comprising:a bus interface for interfacing with a local bus providing multiplexed address and data information to and from a processor, said bus interface having a predetermined bit width and providing a single load point for the computer peripheral dev

이 특허에 인용된 특허 (33)

  1. Kinoshita Tsuneo (Kokubunji JPX), 32-bit personal computer using a bus width converter and a latch for interfacing with 8-bit and 16-bit microprocessors.
  2. Berger Erwin R. (Endicott NY) Olnowich Howard T. (Endwell NY), Architecture converter for slave elements.
  3. Graciotti Alessandro (Cupertino CA), Bus converter.
  4. Aldereguia Alfredo (Boca Raton FL) Amini Nader (Boca Raton FL) Horne Richard L. (Boynton Beach FL) Lohman Terence J. (Boca Raton FL) Tran Cang N. (Boca Raton FL), Bus interface logic for computer system having dual bus architecture.
  5. Osaki Akitoshi (Itami JPX) Nishida Koichi (Itami JPX), Cache memory and bus width control circuit for selectively coupling peripheral devices.
  6. Berger Michael F. (Fort Worth TX) Sawyer Sammy D. (Arlington TX), Co-processor combination.
  7. Curry Sean E. (Pflugerville TX) Dean Mark E. (Austin TX) Faucher Marc R. (South Burlington VT) Peterson James C. (Austin TX) Tanner Howard C. (Austin TX), Connecting a short word length non-volatile memory to a long word length address/data multiplexed bus.
  8. Begun Ralph M. (Boca Raton FL) Bland Patrick M. (Delray Beach FL) Dean Mark E. (Delray Beach FL), Control of pipelined operation in a microcomputer system employing dynamic bus sizing with 80386 processor and 82385 cac.
  9. Mothersole David S. (Austin TX) Crudele Lester M. (Groton MA) Tietjen James L. (Austin TX) Thompson Robert R. (Austin TX), Data processor having dynamic bus sizing.
  10. Murayama Masaki (Fussa JPX) Iida Manjiro (Oume JPX), Data transfer system for a data processing system provided with direct memory access units.
  11. Turlakov Hristo A. (Sofia BGX) Barbutov Venelin G. (Sofia BGX) Machev Stefan S. (Sofia BGX), Device for connecting 8-bit and 16-bit modules to a 16-bit microprocessor system.
  12. Lawler Edward P. (Fairport NY), Digital data apparatus for transferring data between a byte-wide digital data bus and a four byte-wide digital data bus.
  13. Kuroda Hideo (Yokosuka JPX) Mukawa Naoki (Yokohama JPX) Matsuda Kiichi (Kawasaki JPX) Honma Toshihiro (Yokohama JPX) Fukuda Hiroshi (Yokohama JPX), Digital data code conversion circuit for variable-word-length data code.
  14. Hummel Mark D. (Franklin MA) Guyer James M. (Marlboro MA) Epstein David I. (Framingham MA) Keating David L. (Holliston MA) Wallach Steven J. (Richardson TX), Digital data processing system having dual-purpose scratchpad and address translation memory.
  15. Strecker William D. (Harvard MA) Thompson David (Malden MA) Casabona Richard (Stow MA), Dual path bus structure for computer interconnection.
  16. Gaskins Darius D. (Austin TX) Holman ; Jr. Thomas H. (Austin TX) Longwell Michael L. (Austin TX) Matteson Keith D. (Austin TX) Parks Terry J. (Round Rock TX), Dual path memory retrieval system for an interleaved dynamic RAM memory unit.
  17. Schmidt Robert W. (Stafford TX), Eight bit standard connector bus for sixteen bit microcomputer.
  18. Moore Wayne A. (Portland OR), Emulator control sequencer.
  19. Dewa Koichi (Oome JPX), I/O control system for a plurality of peripheral devices.
  20. Takahashi Toshiya (Tokyo JPX) Sato Yoshikuni (Tokyo JPX), Information transferring apparatus.
  21. Maejima Hideo (Hitachi JPX) Masuda Ikuro (Hitachi JPX) Matsumoto Hidekazu (Hitachi JPX) Miyazawa Shyoichi (Narashino JPX), Input/output control device with memory device for storing variable-length data and method of controlling thereof.
  22. Kaufman Phillip A. (Saratoga CA) Washburn Jerry R. (Mission Viejo CA), Integrated and distributed input/output system for a computer.
  23. Bradley John J. (Framingham MA), LSI microprocessor chip with backward pin compatibility and forward expandable functionality.
  24. Kennedy Barry (Santa Ana CA), Method and apparatus for expanding a backplane interconnecting bus in a multiprocessor computer system without additiona.
  25. Turlakov Hristo A. (Sofia BGX) Machev Stefan S. (Sofia BGX) Barbutov Venelin G. (Sofia BGX), Method and device for connecting a 16-bit microprocessor to 8-bit modules.
  26. Goodwin Paul M. (Littleton MA) Thaller Kurt M. (Acton MA), Method for increased performance from a memory stream buffer by eliminating read-modify-write streams from history buffe.
  27. Miyoshi Akio (Oume JPX), Microprocessor having variable data width.
  28. Takenaka Tsutomu (Tokyo JPX), Microprocessor system.
  29. Hu Ming K. (Syracuse NY) Jia Yau G. (Nanjing ; Jiangsu CNX), Microprogram-coupled multiple-microprocessor module with 32-bit byte width formed of 8-bit byte width microprocessors.
  30. Bartlett Peter G. (Davenport IA), Output interface card suitable for use with a programmable logic controller.
  31. Smith Arnold J. (Lawrence MA) Zartarian Martin G. (Boxboro MA) Lyons David J. (New Ipswich NH), Personal computer having a local bus interface to a video circuit.
  32. Belt Steven L. (Stevensville MI) Hovey Scott A. (St. Joseph MI), Suspend/resume capability for a protected mode microprocessor.
  33. Culley Paul R. (Cypress TX), System for controlling the transferring of different widths of data using two different sets of address control and stat.

이 특허를 인용한 특허 (19)

  1. Klein Dean A., Attachment or integration of a BIOS device into a computer system using local bus.
  2. Klein Dean A., Attachment or integration of a BIOS device into a computer system using the system memory data bus.
  3. Eidson,Mark E.; Fleming,Bruce L., Booting from a re-programmable memory on an unconfigured bus.
  4. Meyer, James W.; Cronin, Terry M., Computer system having reduced number of bus bridge terminals.
  5. Usami Hajime,JPX, Data processing system and method for inputting data from storage devices where the data buss width for input depends on the number of memory devices.
  6. Hajime Usami JP, Data processing system for use in conjunction with a font card or the like.
  7. Pielmeier Stefan,DEX, Fast metric calculation for Viterbi decoder implementation.
  8. Bolay, Frederick H.; Nalawadi, Rajeev K., Method and apparatus for remote modification of system configuration.
  9. Bolay, Frederick H.; Nalawadi, Rajeev K., Method and apparatus for remote modification of system configuration.
  10. Bolay, Frederick H.; Nalawadi, Rajeev K., Method and apparatus for remote modification of system configuration setting.
  11. Bolay, Frederick H.; Nalawadi, Rajeev K., Method and apparatus for removable device modification of system configuration.
  12. Bolay, Frederick H.; Nalawadi, Rajeev K., Method and apparatus for removable device modification of system configuration.
  13. Klein Dean A., Method for attachment of a bios device into a computer system using the system memory data bus.
  14. Klein Dean A., Method for attachment or integration of a BIOS device into a computer system using the system memory address and data b.
  15. Klein Dean A., Method for attachment or integration of a bios device into a computer system using a local bus.
  16. Meyer, James W.; Cronin, Terry M., Method of initializing a processor and computer system.
  17. Lo, Chiang; Chen, Tong S; Lin, Kuang-Shin, Method of obtaining the BIOS version date in the windows operating system.
  18. Brown, David A.; Findley, Randy L.; Sonnier, David P.; Thompson, Gary D., Multi-protocol bus system and method of operation thereof.
  19. Brown,David A.; Findley,Randy L.; Sonnier,David P.; Thompson,Gary D., Multi-protocol bus system and method of operation thereof.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로