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Digital data processing methods and apparatus for fault detection and fault tolerance 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-011/00
출원번호 US-0759099 (1996-12-03)
발명자 / 주소
  • Horvath Charles J.
  • Leavitt William I.
  • Tetreault Mark D.
  • Green Gregory M.
  • Churchill Peter C.
출원인 / 주소
  • Stratus Computer, Inc.
대리인 / 주소
    Lahive & Cockfield, LLP
인용정보 피인용 횟수 : 27  인용 특허 : 27

초록

A digital data processing device includes a bus for transmitting signals (e.g., data and/or address information) between plural functional units (e.g., a central processing unit and a peripheral controller). A first such unit includes first and second processing sections that concurrently apply to t

대표청구항

[ In view of the foregoing, what we claim is:] [1.] A fault detecting digital data processing device comprisingA. bus means for transmitting applied signals between plural functional units,B. a first such functional unit including a first processing section for generating a first signal and for appl

이 특허에 인용된 특허 (27)

  1. Pomfret, Stephen T., Bus for data processing system with fault cycle operation.
  2. Reid Robert (Dunstable MA), Central processing apparatus for fault-tolerant computing.
  3. Dynneson Ronald E. (Brighton MA) Hendrie Gardner C. (Marlboro MA), Computer memory apparatus.
  4. Wolff Kenneth T. (Medway MA) Samson Joseph E. (Dover MA) Baty Kurt F. (Medway MA), Computer peripheral control apparatus.
  5. Waldecker Donald E. (Round Rock TX) Wright Charles G. (Round Rock TX), Data processing system with a plurality of processors accessing a common bus to interleaved storage.
  6. Reid Robert (Dunstable MA), Digital data processing apparatus with pipelined memory cycles.
  7. Horvath Charles J. (Concord MA) Leavitt William I. (Grafton MA) Tetreault Mark D. (Northborough MA) Green Gregory M. (Boxborough MA) Churchill Peter C. (Boxborough MA), Digital data processing methods and apparatus for fault detection and fault tolerance.
  8. Hendrie Gardner C. (Marlboro MA) Baty Kurt F. (Medway MA) Dynneson Ronald E. (Brighton MA) Falkoff Daniel M. (Natick MA) Reid Robert (Dunstable MA) Samson Joseph E. (Dover MA) Wolff Kenneth T. (Medwa, Digital data processor apparatus with pipelined fault tolerant bus protocol.
  9. Long William L. (Pembroke MA) Wambach Robert F. (Attleboro MA) Baty Kurt F. (Medway MA) Lamb Joseph M. (Hopedale MA) McNamara John E. (Maynard MA), Digital data processor with fault tolerant peripheral bus communications.
  10. Samson Joseph E. (Dover MA) Wolff Kenneth T. (Medway MA) Reid Robert (Dunstable MA) Hendrie Gardner C. (Marlboro MA) Falkoff Daniel M. (Natick MA) Dynneson Ronald E. (Brighton MA) Clemson Daniel M. (, Digital data processor with high reliability.
  11. Georgiou Christos J. (White Plains NY) Ravn Anders P. (Lyngby DKX), Distributed arbitration for multiple processors.
  12. McDonald John C. (Los Gatos CA) Baichtal James R. (Los Altos CA), Double redundant processor.
  13. Reiff Francis H. (Mannitou Springs CO), Fault tolerant bus.
  14. Hanson David G. (Spring Lake Park MN) Salser Mark A. (Reston VA) Wallace Charles L. (Prior Lake MN), Fault tolerant processor/memory architecture.
  15. Signaigo Robert C. (Oak Lawn IL) Steinlicht Joseph C. (Glen Ellyn IL), Fault tolerant signaling.
  16. Carrubba Francis P. (Sunnyvale CA) Cocke John (Austin TX) Kreitzer Norman H. (Yorktown Heights NY), Hierarchical memory system including separate cache memories for storing data and instructions.
  17. Blum Arnold (Gechingen DEX), Method and apparatus for bus arbitration in a data processing system.
  18. Williams Jeffrey L. (Hopkinton MA), Method and apparatus for detecting selected absence of digital logic synchronism.
  19. Williams Jeffrey L. (Hopkinton MA), Method and apparatus for fault-tolerant computer system having expandable processor section.
  20. Baty Kurt F. (Medway MA) Lamb Joseph M. (Hopedale MA), Method and apparatus for monitoring peripheral device communications.
  21. Jackson Daniel K. (Hillsboro OR), Method and circuit for checking integrated circuit chips.
  22. Stiffler Jack J. (Concord MA) Karp Richard A. (Bedford MA) Nolan ; Jr. James M. (Holliston MA) Budwey Michael J. (Holliston MA) Wallace David A. (Chelmsford MA), Modular computer system.
  23. Danielsen Carl M. (Lake Zurich IL) Dabbish Ezzat A. (Buffalo Grove IL) Puhl Larry C. (Sleepy Hollow IL), Redundant microprocessor control system using locks and keys.
  24. Ossfeldt Bengt E. (lvsjSEX), Stored program controlled real time system including three substantially identical processors.
  25. Irwin John W. (Georgetown TX), System for arbitrating use of I/O bus by co-processor and higher priority I/O units in which co-processor automatically.
  26. Giorcelli Silvano (Turin IT), System for checking two data processors operating in parallel.
  27. Norman John H. (Chandler AZ), Uninterruptable fault tolerant data processor.

이 특허를 인용한 특허 (27)

  1. Long,Finbarr Denis; Ardini,Joseph; Kirkpatrick,Dana A.; O'Keeffe,Michael James, Apparatus and methods for fault-tolerant computing using a switching fabric.
  2. Edwards, Jr., John W., Apparatus and methods for identifying bus protocol violations.
  3. Froeschl, Joachim; Krammer, Josef; Schedl, Anton, Control unit having a main microprocessor and having a processor interface to a bus transceiver unit.
  4. Lanoue, Jean-Claude; Domey, Daniel, Digital indirectly compensated crystal oscillator.
  5. Ghameshlu, Majid; Kainrath, Wolfgang; Knecht, Stephan, Duplicable processor device.
  6. Baleani, Massimo; Losi, Marco; Ferrari, Alberto; Mangeruca, Leonardo, Electronic system for detecting a fault.
  7. Somers, Jeffrey S.; Huang, Wen-Yi; Tetreault, Mark D.; Wegner, Timothy M., Fault-tolerant computer system with voter delay buffer.
  8. Suffin, A. Charles; Amato, Joseph S.; Joyce, Paul, Fault-tolerant maintenance bus architecture.
  9. Suffin, A. Charles, Fault-tolerant maintenance bus protocol and method for using the same.
  10. Watabe Toru,JPX ; Sakurai Yasutomo,JPX ; Kishino Takumi,JPX ; Hirose Yoshio,JPX ; Odahara Koichi,JPX ; Nonomura Kazuhiro,JPX ; Takeno Takumi,JPX ; Katoh Shinya,JPX ; Noda Takato,JPX, Information processing system.
  11. Manoni,Vittorio, Inherently fail safe processing or control apparatus.
  12. Chouinard, Luc; Coomber, David George; Vieregge, Richard Charles; Janz, Emmanuelle Marie Josèphe, Layer 2 and 3 latching loopbacks on a pluggable transceiver.
  13. Dao-Long Chen, Method and Circuit for testing devices with serial data links.
  14. Somers, Jeffrey; Alden, Andrew; Edwards, John, Method and apparatus for efficiently moving portions of a memory block.
  15. Abdelnour George Michel ; Bond Arthur Latimer ; Downes Robert W. ; Potter ; Jr. Kenneth H. ; Yu Frederick K., Method and apparatus for interface dual modular redundancy.
  16. Somers, Jeffrey S.; Tetreault, Mark D.; Wegner, Timothy M., Method and system for upgrading fault-tolerant systems.
  17. Kuntzsch Claus,DEX ; Mayer Frank,DEX, Method for the monitoring of integrated circuits.
  18. Tetreault,Mark, Methods and apparatus for computer bus error termination.
  19. Coomber, David George; Janz, Emmanuelle Marie Josèphe; Curry, Jason, Network services testing with pluggable transceivers.
  20. Takita Masatoshi,JPX ; Ohnishi Kazuei,JPX ; Saito Takamitsu,JPX, Redundant apparatus.
  21. James L. Petivan ; Jonathan K. Lundell ; Don C. Lundell, Redundant clock system and method for use in a computer.
  22. Deog-su Han KR, Self-diagnostic method for detecting faults in a transceiver within a wireless receiving unit of a base transceiver station.
  23. Graham, Simon P., System and method for operating a SCSI bus with redundant SCSI adaptors.
  24. Nelvin, Robert E.; Tetreault, Mark D.; Alden, Andrew; Dolaty, Mohsen; Edwards, Jr., John W.; Kement, Michael W.; MacLeod, John R., System and method for operating a system with redundant peripheral bus controllers.
  25. Fiorentino, Richard D.; Kaman, Charles H.; Troiani, Mario; Muench, Erik, System for cross-host, multi-thread session alignment.
  26. Petivan James L. ; Lundell Jonathan K. ; Lundell Don C., Triple modular redundant computer system.
  27. Petivan James L. ; Lundell Jonathan K. ; Lundell Don C., Triple modular redundant computer system and associated method.
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