[특허]Field effect transistor and CMOS element having dopant exponentially graded in channel

Field effect transistor and CMOS element having dopant exponentially graded in channel 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-027/12 H01L-027/105 H01L-029/786
출원번호	US-0782251 (1997-01-14)
우선권정보	JP-0105915 (1996-04-25)
발명자 / 주소	Adan Alberto Oscar,JPX Kaneko Seiji,JPX
출원인 / 주소	Sharp Kabushiki Kaisha, JPX
대리인 / 주소	Nixon & Vanderhye P.C.
인용정보	피인용 횟수 : 92 인용 특허 : 0

초록 ▼

A field effect transistor is fabricated on an SOI substrate. N-type source and drain regions are arranged apart from each other in a semiconductor thin film of the SOI substrate. A P-type channel region is formed between the source and drain regions. Moreover, a gate electrode is formed over the channel region to cover the channel region through a gate oxide film. Extreme portions of the channel region, adjacent to the source and drain regions, have higher doping concentrations than in a center portion thereof. Furthermore, the gradient of the doping profile in the channel region is adjusted so as to reduce the current gain of a parasitic transistor in the field effect transistor. This structure enables a reduction of the channel length of the field effect transistor to the sub-half-micron order without deteriorating the electrical characteristics of the field effect transistor.

대표청구항 ▼

[ What is claimed is:] [1.] A field effect transistor comprising:a channel region of a first conductivity type formed in a superficial semiconductor layer overlying an electrically insulating substrate;a source region and a drain region of a second conductivity type different from said first conductivity type, said source and drain regions being disposed with said channel region therebetween;a highly doped portion provided in said channel region at least in a section adjacent to said source region, said highly doped portion having a doping profile N(x) formed so that a concentration of impurities of said first conductivity type is substantially monotonically lowered toward a center portion of said channel region; anda gate electrode insulated from said channel region by an electrically insulating layer,wherein said doping profile N(x) substantially conforms to the expression: EQU N(x)=N.sub.0 +N.sub.B0 .multidot.exp [-(.eta..multidot.x).sup.g)] re N.sub.0 is a minimum doping level, N.sub.B0 is a maximum doping level, x is a displacement in .mu.m from said highly doped portion toward said center portion of said channel region, g is a doping profile sharpness, and .eta. is a doping profile gradient coefficient.

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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

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연합인증

Field effect transistor and CMOS element having dopant exponentially graded in channel 원문보기

초록 ▼

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Field effect transistor and CMOS element having dopant exponentially graded in channel 원문보기

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