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Semiconductor device having a projecting element region 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/76
  • H01L-029/94
  • H01L-031/062
출원번호 US-0527636 (1995-09-13)
우선권정보 JP-0232506 (1995-09-11)
발명자 / 주소
  • Mizuno Tomohisa,JPX
  • Ushiku Yukihiro,JPX
  • Yoshimi Makoto,JPX
  • Terauchi Mamoru,JPX
  • Kawanaka Shigeru,JPX
출원인 / 주소
  • Kabushiki Kaisha Toshiba, JPX
대리인 / 주소
    Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
인용정보 피인용 횟수 : 104  인용 특허 : 0

초록 ▼

The present invention provides a semiconductor device which includes a substrate having a projection-shaped semiconductor element region, a gate electrode formed through a gate insulating film on the upper face and side face of the element region, and a first conductivity type source region and drai

대표청구항 ▼

[ What is claimed is:] [1.] A semiconductor device comprising:a substrate having a semiconductor element region of a projection shape;a gate electrode formed on an upper surface and a side surface of said element region via a gate insulation film; anda source region and a drain region, of a first co

이 특허를 인용한 특허 (104)

  1. Kavalieros,Jack T.; Shah,Uday; Rachmady,Willy; Doyle,Brian S., Apparatus and method for selectively recessing spacers on multi-gate devices.
    상세보기
  2. Lindert, Nick; Cea, Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
    상세보기
  3. Doyle, Brian S.; Jin, Been-Yih; Kavalieros, Jack T.; Datta, Suman; Brask, Justin K.; Chau, Robert S., CMOS devices with a single work function gate electrode and method of fabrication.
    상세보기
  4. Brask, Justin K.; Datta, Suman; Doczy, Mark L.; Blackwell, James M.; Metz, Matthew V.; Kavalieros, Jack T.; Chau, Robert S., Dielectric interface for group III-V semiconductor device.
    상세보기
  5. Adkisson,James W.; Agnello,Paul D.; Ballantine,Arne W.; Divakaruni,Rama; Jones,Erin C.; Rankin,Jed H., Double gate trench transistor.
    상세보기
  6. Kavalieros, Jack T.; Mukherjee, Niloy; Dewey, Gilbert; Somasekhar, Dinesh; Doyle, Brian S., Embedded memory cell and method of manufacturing same.
    상세보기
  7. Adan,Alberto O, Field effect transistor and fabrication method thereof.
    상세보기
  8. Popp,Martin; Richter,Frank; Temmler,Dietmar; Wich Glasen,Andreas, Field effect transistor and method for fabricating it.
    상세보기
  9. Radosavljevic, Marko; Datta, Suman; Doyle, Brian S.; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Majumdar, Amian; Chau, Robert S., Field effect transistor with metal source/drain regions.
    상세보기
  10. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
    상세보기
  11. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
    상세보기
  12. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
    상세보기
  13. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
    상세보기
  14. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
    상세보기
  15. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
    상세보기
  16. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
    상세보기
  17. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
    상세보기
  18. Kim, Keun-Nam; Yang, Hung-Mo; Lee, Choong-Ho, Fin FET and method of fabricating same.
    상세보기
  19. Kim, Keun-Nam; Yang, Hung-Mo; Lee, Choong-Ho, Fin FET and method of fabricating same.
    상세보기
  20. Kim, Keun-Nam; Yang, Hung-Mo; Lee, Choong-Ho, Fin FET and method of fabricating same.
    상세보기
  21. Kim, Keun-Nam; Yang, Hung-Mo; Lee, Choong-Ho, Fin FET and method of fabricating same.
    상세보기
  22. Kim, Keun-Nam; Yang, Hung-Mo; Lee, Choong-Ho, Fin FET and method of fabricating same.
    상세보기
  23. Lee,Choong Ho; Park,Dong Gun; Youn,Jae Man; Lee,Chul, Fin FET structure.
    상세보기
  24. Morikado,Mutsuo, Fin semiconductor device and method for fabricating the same.
    상세보기
  25. Morikado,Mutsuo, Fin semiconductor device and method for fabricating the same.
    상세보기
  26. Tsai, Chun Hsiung; Chong, Lai-Wan; Lee, Chien-Wei; Chen, Kei-Wei, FinFET structure and method for manufacturing thereof.
    상세보기
  27. Lee,Deok Hyung; Lee,Byeong Chan; Choi,Si Young; Jung,In Soo, Finfets having first and second gates of different resistivities.
    상세보기
  28. Strain, Robert J.; Asenov, Asen, Fluctuation resistant FinFET.
    상세보기
  29. An, Judy Xilin; Krivokapic, Zoran; Wang, Haihong; Yu, Bin, Germanium MOSFET devices and methods for making same.
    상세보기
  30. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors.
    상세보기
  31. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
    상세보기
  32. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
    상세보기
  33. Lee,Deok Hyung; Lee,Byeong Chan; Choi,Si Young; Kim,Taek Jung; Son,Yong Hoon; Jung,In Soo, Integrated circuit field effect transistors including channel-containing fin having regions of high and low doping concentrations.
    상세보기
  34. Chang, Peter L. D., Integration of planar and tri-gate devices on the same substrate.
    상세보기
  35. Chang,Peter L. D., Integration of planar and tri-gate devices on the same substrate.
    상세보기
  36. Ando, Yoshiyuki, Ion implantation methods and transistor cell layout for fin type transistors.
    상세보기
  37. Datta,Suman; Doyle,Brian S.; Chau,Robert S.; Kavalieros,Jack; Zheng,Bo; Hareland,Scott A., Method and apparatus for improving stability of a 6T CMOS SRAM cell.
    상세보기
  38. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
    상세보기
  39. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
    상세보기
  40. Shah,Uday; Doyle,Brian S.; Brask,Justin K.; Chau,Robert S., Method of fabricating a multi-cornered film.
    상세보기
  41. Ahn, Young Joon; Park, Dong Gun; Lee, Choong Ho; Kang, Hee Soo, Method of forming fin field effect transistor using damascene process.
    상세보기
  42. Doyle,Brian S.; Datta,Suman; Kavalieros,Jack T.; Majumdar,Amlan, Method of ion implanting for tri-gate devices.
    상세보기
  43. Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Chau, Robert S., Method of patterning a film.
    상세보기
  44. Mathew, Leo; Noble, Ross E.; Rai, Raghaw S., Method to control uniformity/composition of metal electrodes, silicides on topography and devices using this method.
    상세보기
  45. Lee,Deok Hyung; Choi,Si Young; Lee,Byeong Chan; Son,Yong Hoon; Jung,In Soo, Methods for fabricating fin field effect transistors using a protective layer to reduce etching damage.
    상세보기
  46. Lee, Deok Hyung; Lee, Byeong Chan; Choi, Si Young; Kim, Taek Jung; Son, Yong Hoon; Jung, In Soo, Methods for fabricating integrated circuit field effect transistors including channel-containing fin having regions of high and low doping concentrations.
    상세보기
  47. Brask, Justin K.; Kavalieros, Jack; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S.; Doyle, Brian S., Methods for patterning a semiconductor film.
    상세보기
  48. Manning H. Montgomery, Methods of forming SOI insulator layers and methods of forming transistor devices.
    상세보기
  49. Manning H. Montgomery, Methods of forming SOI insulator layers, methods of forming transistor devices, and semiconductor devices and assemblies.
    상세보기
  50. Manning H. Montgomery, Methods of forming SOI insulator layers, methods of forming transistor devices, and semiconductor devices and assemblies.
    상세보기
  51. Manning H. Montgomery, Methods of forming SOI insulator layers, methods of forming transistor devices, and semiconductor devices and assemblies.
    상세보기
  52. Kavalieros, Jack T.; Brask, Justin K.; Datta, Suman; Doyle, Brian S.; Chau, Robert S., Multigate device with recessed strain regions.
    상세보기
  53. Brask,Justin K.; Kavalieros,Jack T.; Doyle,Brian S.; Chau,Robert S., Non-planar microelectronic device having isolation element to mitigate fringe effects and method to fabricate same.
    상세보기
  54. Doyle,Brian S; Datta,Suman; Jin,Been Yih; Zelick,Nancy M; Chau,Robert, Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow.
    상세보기
  55. Hareland,Scott A.; Chau,Robert S.; Doyle,Brian S.; Datta,Suman; Jin,Been Yih, Nonplanar device with stress incorporation layer and method of fabrication.
    상세보기
  56. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
    상세보기
  57. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
    상세보기
  58. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
    상세보기
  59. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
    상세보기
  60. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
    상세보기
  61. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
    상세보기
  62. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
    상세보기
  63. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
    상세보기
  64. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
    상세보기
  65. Hareland,Scott A.; Chau,Robert S.; Doyle,Brian S.; Rios,Rafael; Linton,Tom; Datta,Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
    상세보기
  66. Brask, Justin K.; Dovle, Brian S.; Kavalleros, Jack; Doczy, Mark; Shah, Uday; Chau, Robert S., Nonplanar transistors with metal gate electrodes.
    상세보기
  67. Brask,Justin K.; Doyle,Brian S.; Kavalieros,Jack; Doczy,Mark; Shah,Uday; Chau,Robert S., Nonplanar transistors with metal gate electrodes.
    상세보기
  68. Kavalieros, Jack T.; Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Datta, Suman; Doczy, Mark L.; Metz, Matthew V.; Chau, Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
    상세보기
  69. Kavalieros,Jack T.; Brask,Justin K.; Doyle,Brian S.; Shah,Uday; Datta,Suman; Doczy,Mark L.; Metz,Matthew V.; Chau,Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
    상세보기
  70. Lee, Jong-Ho, Saddle type MOS device.
    상세보기
  71. Rachmady, Willy; Shah, Uday; Kavalieros, Jack T.; Doyle, Brian S., Selective anisotropic wet etching of workfunction metal for semiconductor devices.
    상세보기
  72. Kim, Jung-Hwan; Leam, Hun-Hyeoung; Kim, Tae-Hyun; Nam, Seok-Woo; Namkoong, Hyun; Kim, Yong-Seok; Yu, Tea-Kwang, Semiconductor device and method of fabricating the same.
    상세보기
  73. Kim, Jung-Hwan; Leam, Hun-Hyeoung; Kim, Tae-Hyun; Nam, Seok-Woo; Namkoong, Hyun; Kim, Yong-Seok; Yu, Tea-Kwang, Semiconductor device and method of fabricating the same.
    상세보기
  74. Kim, Jung-Hwan; Leam, Hun-Hyeoung; Kim, Tae-Hyun; Nam, Seok-Woo; Namkoong, Hyun; Kim, Yong-Seok; Yu, Tea-Kwang, Semiconductor device and method of fabricating the same.
    상세보기
  75. Mueller, Markus; Singanamalla, Raghunath, Semiconductor device and method of manufacturing a semiconductor device.
    상세보기
  76. Nishi, Masahiro, Semiconductor device and method of manufacturing semiconductor device.
    상세보기
  77. Nishi, Masahiro, Semiconductor device and method of manufacturing semiconductor device.
    상세보기
  78. Inaba, Satoshi; Ohuchi, Kazuya, Semiconductor device having MIS field effect transistors or three-dimensional structure.
    상세보기
  79. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
    상세보기
  80. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
    상세보기
  81. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
    상세보기
  82. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
    상세보기
  83. Manning H. Montgomery, Semiconductor devices and assemblies.
    상세보기
  84. Manning H. Montgomery, Semiconductor devices comprising semiconductive material substrates and insulator layers over the substrates.
    상세보기
  85. You, Jung-Gun; Um, Myung-Yoon; Park, Young-Joon; Lee, Jeong-Hyo; Ha, Ji-Yong; Hwang, Jun-Sun, Semiconductor devices having gate structures with skirt regions.
    상세보기
  86. Izumida, Takashi; Ito, Sanae; Kanemura, Takahisa, Semiconductor manufacturing method and semiconductor device.
    상세보기
  87. Izumida, Takashi; Ito, Sanae; Kanemura, Takahisa, Semiconductor manufacturing method and semiconductor device.
    상세보기
  88. Izumida, Takashi; Ito, Sanae; Kanemura, Takahisa, Semiconductor manufacturing method and semiconductor device.
    상세보기
  89. Doyle,Brian S; Rakshit,Titash; Chau,Robert S; Datta,Suman; Brask,Justin K; Shah,Uday, Stacked multi-gate transistor design and method of fabrication.
    상세보기
  90. Hudait, Mantu K.; Shaheen, Mohamad A.; Chow, Loren A.; Tolchinsky, Peter G.; Fastenau, Joel M.; Loubychev, Dmitri; Liu, Amy W. K., Stacking fault and twin blocking barrier for integrating III-V on Si.
    상세보기
  91. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
    상세보기
  92. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
    상세보기
  93. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
    상세보기
  94. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
    상세보기
  95. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
    상세보기
  96. Doyle, Brian S.; Jin, Been-Yih; Kavalieros, Jack T.; Datta, Suman, Substrate band gap engineered multi-gate pMOS devices.
    상세보기
  97. Tsai, Chun Hsiung; Chan, Chien-Tai; Yeh, Mao-Rong; Lin, Da-Wen, Techniques for FinFET doping.
    상세보기
  98. Tsai, Chun Hsiung; Chan, Chien-Tai; Yeh, Mao-Rong; Lin, Da-Wen, Techniques for FinFET doping.
    상세보기
  99. Ban,Ibrahim; Chang,Peter L. D., Tri-gate integration with embedded floating body memory cell using a high-K dual metal gate.
    상세보기
  100. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
    상세보기
  101. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
    상세보기
  102. Metz,Matthew V.; Datta,Suman; Doczy,Mark L.; Kavalieros,Jack T.; Brask,Justin K.; Chau,Robert S., Uniform silicide metal on epitaxially grown source and drain regions of three-dimensional transistors.
    상세보기
  103. Oh, Chang-Woo; Park, Dong-Gun; Lee, Sung-Young; Choe, Jeong-Dong; Kim, Dong-Won, Vertical channel fin field-effect transistors having increased source/drain contact area and methods for fabricating the same.
    상세보기
  104. Kim, Keun-Nam; Yang, Hung-Mo; Lee, Choong-Ho, fin FET and method of fabricating same.
    상세보기

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