초록 ▼

A tunable phase generator is disclosed suitable for use in integrated circuits. The phase generator includes a delay element wherein passive resistors and conductors are employed to provide relatively constant delays despite changes in operating temperatures and voltages. The phase generator is driv

A tunable phase generator is disclosed suitable for use in integrated circuits. The phase generator includes a delay element wherein passive resistors and conductors are employed to provide relatively constant delays despite changes in operating temperatures and voltages. The phase generator is driven by a clock signal and generates therefrom a self-resettable output signal pulse with a selectable pulse width no longer than the width of the clock signal. The variable widths are provided by varying the delays of the delay elements and adding combinational logic between respective delay elements and at the input and output of the phase generator that ensure that, in most situations, the output signal pulse is reset after a delay that is independent of the pulse width of the clock signal. Delays are lengthened by decreasing the current available to a delay element for charging the capacitors. Delays are decreased by disconnecting at least some of the capacitors so that the corresponding delay element has virtually no delay.

대표청구항 ▼

[ What is claimed is:] [1.] A tunable pulse generator, comprising:an input port for receiving a stimulus signal;a chain of delay elements; anda logic circuit coupled to the input port and an output of the chain of delay elements for generating a pulse in response to a predefined logic transition in

[ What is claimed is:] [1.] A tunable pulse generator, comprising:an input port for receiving a stimulus signal;a chain of delay elements; anda logic circuit coupled to the input port and an output of the chain of delay elements for generating a pulse in response to a predefined logic transition in the stimulus signal, where the length of the generated pulse is governed by a delay time associated with the chain of delay elements, and wherein the pulse automatically terminates after a tunable pulse duration;at least one of the delay elements including;a tunable inverter structure including a plurality of inverters with common inputs coupled to a first signal; one subset of the plurality of inverters having an output coupled to a first output node via a respective fuse; another subset having an output coupled directly to the first output node; wherein the respective fuse has a respective open/closed circuit status and an output of the tunable inverter structure is a second signal having a current strength that is a function of the open/closed circuit status of the respective fuses; anda delay structure including a passive resistor with an input coupled to receive the second signal and an associated resistance that varies insignificantly as a function of operating temperature and operating voltage, and a load circuit with an input coupled to an output of the passive resistor and an associated capacitance determined by gate capacitances of transistors composing the load circuit, the transistors being connected so that the associated capacitance varies insignificantly as a function of operating temperature and operating voltage; wherein the resistance and capacitance determine in accordance with current strength of the second signal a delay associated with the delay structure that determines voltage profile characteristics of a delay output signal generated by the delay structure in response to transitions of the second signal.