초록 ▼

This disclosure provides a multiple chip assembly where multiple chips are stacked on top of one another using relatively low melting temperature solder balls. Preferably, the chips (either packages or flip chip attachment) are each mounted to a substrate which is larger in lateral surface area than

This disclosure provides a multiple chip assembly where multiple chips are stacked on top of one another using relatively low melting temperature solder balls. Preferably, the chips (either packages or flip chip attachment) are each mounted to a substrate which is larger in lateral surface area than the associated chip. Each substrate thus has a free area, not masked by the chip, which is utilized to mount a vertically-adjacent substrate. Within this free area, solder balls connect the substrates to provide for vertical logic bus propagation through the assembly and vertical heat dissipation. The solder balls are made to have a relatively low melting temperature, permitting interconnection between chip/substrate layers without affecting connection between chip and substrate or with an intervening carrier. At the same time, the layers are compressed together during such interconnection to bring a thermal transport layer in contact between the bottom of each substrate and the chip of an underlying layer, to facilitate lateral heat dissipation.

대표청구항 ▼

[ We claim:] [1.] A multiple chip assembly, comprising:a first integrated circuit mounted upon a first substrate;a second integrated circuit mounted upon a second substrate, the second integrated circuit having a height associated with it, the second integrated circuit also being overlapped by the s

[ We claim:] [1.] A multiple chip assembly, comprising:a first integrated circuit mounted upon a first substrate;a second integrated circuit mounted upon a second substrate, the second integrated circuit having a height associated with it, the second integrated circuit also being overlapped by the second substrate in at least one of width and length dimensions, such that the second substrate presents a free area not masked by the second integrated circuit; andsolder bumps which provide electrical interconnection between the first and second substrates, the solder bumps being at least as tall as the height of the second integrated circuit to thereby electrically mount the first substrate in a stacked relation above the second integrated circuit;a thermal transport layer in between and in contact with each of the second integrated circuit and the first substrate;whereinthe second substrate includes (on a side of the second substrate which mounts the second integrated circuit), in the free area, electrical terminations for electrical interconnection to the first substrate,the first substrate includes corresponding electrical terminations for electrical interconnection to the second substrate, andthe solder bumps connect the electrical terminations of the second substrate with the corresponding electrical terminations of the first substrate.