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Semiconductor device having a bump structure and test electrode 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/50
  • H01L-029/78
  • H01L-023/54
출원번호 US-0679074 (1996-07-12)
우선권정보 KR-0020848 (1995-07-14)
발명자 / 주소
  • Kim Seong Jin,KRX
출원인 / 주소
  • LG Electronics Inc., KRX
대리인 / 주소
    Morgan, Lewis & Bockius LLP
인용정보 피인용 횟수 : 113  인용 특허 : 8

초록

A bump structure of a semiconductor device includes at least one pad electrode formed on a semiconductor substrate; a test electrode formed on the semiconductor substrate, the pad electrode and the test electrode being located separately from one another; a passivation layer formed on an area of the

대표청구항

[ What is claimed is:] [1.] A bump structure of a semiconductor device, the bump structure comprising:at least one pad electrode on a semiconductor substrate;a test electrode on the semiconductor substrate, the pad electrode and the test electrode being located separately from one another;a passivat

이 특허에 인용된 특허 (8)

  1. Nye ; III Henry A. (Bedford NY) Roeder Jeffrey F. (Brookfield CT) Tong Ho-Ming (Yorktown Heights NY) Totta Paul A. (Poughkeepsie NY), Electroplated solder terminal.
  2. Takada Norimasa (Tokyo JPX), Flip chip type semiconductor device.
  3. Sawai Akiyoshi (Hyogo JPX) Shimamoto Haruo (Hyogo JPX) Tachikawa Toru (Hyogo JPX) Shibata Jun (Hyogo JPX), Plastic molded semiconductor package.
  4. Seppala Bryan R. (Apple Valley MN) Backer Todd G. (Apple Valley MN) Maier Lothar (Eden Prairie MN), Process for manufacturing a semiconductor device bump electrode using a rapid thermal anneal.
  5. Hosomi Eiichi (Kawasaki JPX) Takubo Chiaki (Yokohama JPX) Tazawa Hiroshi (Ichikawa JPX) Miyamoto Ryouichi (Kawasaki JPX) Arai Takashi (Oita JPX) Shibasaki Koji (Kawasaki JPX), Semiconductor device comprising fine bump electrode having small side etch portion and stable characteristics.
  6. Gelsing Richardus Johannes Henricus (Eindhoven NL) VAN Steensel Kees (Eindhoven NL), Semiconductor device with multi-layered metal interconnections.
  7. Bhattacharya Somnath (Wappingers Falls NY) Hu Shih-Ming (Hopewell Junction NY) Koopman Nicholas G. (Hopewell Junction NY) Oldakowski Chester C. (Poughkeepsie NY), Solder mound formation on substrates.
  8. Sato Hiroya (Tenri JPX), Vertical type construction transistor.

이 특허를 인용한 특허 (113)

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  34. Paul Davis Bell, Integrated circuit having wirebond pads suitable for probing.
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  40. Lin, Mou-Shiung, Metallization structure over passivation layer for IC chip.
  41. Bohr,Mark T.; Martell,Robert W., Method and apparatus for improved power routing.
  42. Bohr,Mark T.; Martell,Robert W., Method and apparatus for improved power routing.
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  44. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Method for fabricating chip package with die and substrate.
  45. Lee, Jin-Yuan; Chou, Chien-Kang; Lin, Shih-Hsiung; Kuo, Hsi-Shan, Method for fabricating circuit component.
  46. Perry,Guy, Method of forming a bond pad structure.
  47. Seshan,Krishna, Method of forming segmented ball limiting metallurgy.
  48. Lin, Shih-Hsiung; Lin, Mou-Shiung, Method of joining chips utilizing copper pillar.
  49. Lin, Shih-Hsiung; Lin, Mou-Shiung, Method of joining chips utilizing copper pillar.
  50. Dubin,Valery M.; Moon,Peter K., Method of protecting a seed layer for electroplating.
  51. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
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  55. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  56. Lee, Jin-Yuan; Chen, Ying-chih, Method of wire bonding over active area of a semiconductor circuit.
  57. Lin, Mou-Shiung; Lee, Jin-Yuan, Non-cyanide gold electroplating for fine-line gold traces and gold pads.
  58. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection process and structures.
  59. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  60. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  61. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
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  73. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection structures.
  74. Lin, Mou-Shiung; Lee, Jin-Yuan; Lei, Ming-Ta; Huang, Ching-Cheng, Post passivation metal scheme for high-performance integrated circuit devices.
  75. Kasukabe, Susumu; Hasebe, Akio, Probing device and manufacturing method thereof, as well as testing apparatus and manufacturing method of semiconductor with use thereof.
  76. Kasukabe, Susumu; Hasebe, Akio, Probing device and manufacturing method thereof, as well as testing apparatus and manufacturing method of semiconductor with use thereof.
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  78. Huang, Ching-Cheng; Lin, Chuen-Jye; Lei, Ming-Ta; Lin, Mou-Shiung, Reliable metal bumps on top of I/O pads after removal of test probe marks.
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  100. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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