초록 ▼

A multiple access digital up converter/modulator includes selectors (1606, 1608) having inputs (1602, 1604) and outputs coupled to first and second interpolating filters (1610, 1626). The output of the first interpolating filter is selectively coupled to a first mixer (1612) and a first adder (1622)

A multiple access digital up converter/modulator includes selectors (1606, 1608) having inputs (1602, 1604) and outputs coupled to first and second interpolating filters (1610, 1626). The output of the first interpolating filter is selectively coupled to a first mixer (1612) and a first adder (1622), the first adder also receiving a first phase value and the output is coupled to a first phase accumulator (1616) the output of which is coupled to a first sinusoid generator (1614) and selectively coupled to a second sinusoid generator (1630). The output of each of the first and second mixers are selectively coupled to an output adder (1634) and to inputs of the first and second mixers. The output of the second interpolating filter (1626) is selectively coupled to a second mixer (1628) and a second adder (1638), which also receives a second phase value and the output of which is coupled to a second phase accumulator (1640) the output of which is selectively coupled to the second sinusoid generator. The output of each of the first and second mixers are selectively coupled to an output adder (1634).

대표청구항 ▼

[ What is claimed is:] [1.] An up converter/modulator comprising:a first selector and a second selector each having a plurality of inputs and an output, the outputs of each of the first and second selectors being coupled to a first interpolating filter and a second interpolating filter, respectively

[ What is claimed is:] [1.] An up converter/modulator comprising:a first selector and a second selector each having a plurality of inputs and an output, the outputs of each of the first and second selectors being coupled to a first interpolating filter and a second interpolating filter, respectively;an output of the first interpolating filter being selectively coupled to a first mixer and a first adder, the first adder being further coupled to receive a first phase value and an output of which is coupled to a first phase accumulator;an output of the first phase accumulator being coupled to a first sinusoid generator and selectively coupled to a second sinusoid generator;an output of the second interpolating filter being coupled to a second mixer and a second adder, the second adder being further coupled to receive a second phase value and an output of which is coupled to a second phase accumulator;an output of each of the first and second mixers being coupled to an output adder; andan output of the second phase accumulator being selectively coupled to the second sinusoid generator.