초록 ▼

The present invention concerns a method of generating code for a programmable processor and comprises several steps. The first step is representing the processor as a directed bipartite graph with first and second sets of vertices and with edges, the graph comprising essentially all information abou

The present invention concerns a method of generating code for a programmable processor and comprises several steps. The first step is representing the processor as a directed bipartite graph with first and second sets of vertices and with edges, the graph comprising essentially all information about an instruction set and hardware of the processor, the first set of vertices representing storage elements in the processor, and the second set of vertices representing operations in the processor. The second step includes linking the graph to tools and libraries required for generating code for the processor. The last step is executing the required code generation phases, whereby the required information about the processor is extracted from the graph. The present invention also concerns the application of this method.

대표청구항 ▼

[ What is claimed is:] [15.] A retargetable code generator for generating code for programmable processors being embedded in an electronic system comprising:an electronic system with an embedded programmable processor, first tools to build a directed bipartite graph with vertices and edges which int

[ What is claimed is:] [15.] A retargetable code generator for generating code for programmable processors being embedded in an electronic system comprising:an electronic system with an embedded programmable processor, first tools to build a directed bipartite graph with vertices and edges which internally represents said programmable processor, said graph comprising essentially all information about the instruction set and the hardware of said processor and having first and second sets of vertices, said first set of vertices representing storage elements in said processor, and said second set of vertices representing micro-operations in said processor, said edges represent valid connections between said micro-operations and said storage elements,second tools and libraries required to generate code for said processor, andmeans to link said graph to said second tools and said libraries, whereby the information about said processor required during code generation is extracted from said graph.