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An eight-bit RISC based microcontroller includes an eight-bit register file having a dedicated arithmetic logic unit (ALU), in addition to a general purpose eight-bit ALU. The register file further includes means for combining a pair of registers to provide a logical sixteen-bit register for indirec

An eight-bit RISC based microcontroller includes an eight-bit register file having a dedicated arithmetic logic unit (ALU), in addition to a general purpose eight-bit ALU. The register file further includes means for combining a pair of registers to provide a logical sixteen-bit register for indirect addressing. The dedicated ALU is a sixteen-bit ALU which provides certain arithmetic functions for the register pair, thus alleviating the computational burdens that would otherwise be imposed on the general purpose eight-bit ALU. A further feature of the invention is the inclusion of a paging register which is combined with the contents of the logical sixteen-bit register to provide an even greater addressing range. Yet another feature of the eight-bit microcontroller of the present invention is the means for directly reading and writing to any bit position within the register file with a single instruction. This avoids having to perform various load, shift and/or masking operations needed by prior art microcontrollers.

대표청구항 ▼

[ We claim:] [1.] A microcontroller having a Harvard architecture, comprising:a program bus;a program memory store for storing programs;an instruction decoder unit coupled to said program store via said program bus;an eight-bit data bus separate from said program bus;randomly accessible memory separ

[ We claim:] [1.] A microcontroller having a Harvard architecture, comprising:a program bus;a program memory store for storing programs;an instruction decoder unit coupled to said program store via said program bus;an eight-bit data bus separate from said program bus;randomly accessible memory separate from said program store coupled to said eight-bit data bus;a register file coupled to said eight-bit data bus, said register file having a plurality of eight-bit registers, said register file further having means for combining two of said eight-bit registers to be accessed as a single logical sixteen-bit register;a general purpose ALU coupled to receive the contents of two of said eight-bit registers, said general purpose ALU having an output coupled to said eight-bit data bus;a direct-address bus coupling said program execution unit to directly access said data store and said register file during program execution; andan indirect-address bus providing said register file with indirect data access to said randomly accessible memory during program execution;said register file further including a dedicated ALU coupled to said means for combining in order to perform arithmetic functions on a logical sixteen-bit register accessed through said combining means;said indirect-address bus having address-receiving means for receiving a sixteen-bit value from said combining means, thereby providing sixteen-bit indirect addressing.