초록 ▼

A system bus architecture for intermodular communications is disclosed. The system bus architecture comprises a backplane bus with associated memory and a plurality of control registers. A master system processor module is coupled to the backplane bus via a master bus controller. The master system p

A system bus architecture for intermodular communications is disclosed. The system bus architecture comprises a backplane bus with associated memory and a plurality of control registers. A master system processor module is coupled to the backplane bus via a master bus controller. The master system processor module contains a central processing unit in selective communication the master bus controller. A plurality of slave modules are also coupled to the backplane bus via respective slave bus controllers. Each of the slave modules has a slave central processing unit in selective communication the slave bus controller. The master and slave bus controllers are in selective communication with the bus memory, the plurality of control registers, and the respective central processing units, to transmit and receive data through the backplane bus.

대표청구항 ▼

[ Having thus described my invention, what we claim as new and desire to secure by letters patent is as follows:] [1.] A system bus architecture for intermodular communications, comprising:a backplane bus;a master system processor module coupled to said backplane bus via a master bus controller, sai

[ Having thus described my invention, what we claim as new and desire to secure by letters patent is as follows:] [1.] A system bus architecture for intermodular communications, comprising:a backplane bus;a master system processor module coupled to said backplane bus via a master bus controller, said master system processor module having a central processing unit in selective communication with said master bus controller;a plurality of slave modules each coupled to said backplane bus via a slave bus controller, each of said plurality of slave modules having a slave central processing unit in selective communication with said slave bus controller;a shared bus memory in communication with said backplane bus for storing data communicated from said master system processor module to said plurality of slave modules; anda plurality of registers for permitting access to said shared bus memory by said master system processor module when said shared bus memory is not being accessed by one of said slave modules and denying access to said shared memory by said master system processor module when said shared bus memory is being accessed by one of said slave modules,said master and slave bus controllers being in selective communication with said shared bus memory, said plurality of registers, and respective central processing units, to communicate data through said shared bus memory and said backplane bus.