초록 ▼

A method for making multilevel electrical interconnections having a planar intermetal dielectric (IMD) with low dielectric constant k and good thermal conductivity was achieved. The method involves patterning an electrically conductive layer to form metal lines on which is deposited an anisotropic p

A method for making multilevel electrical interconnections having a planar intermetal dielectric (IMD) with low dielectric constant k and good thermal conductivity was achieved. The method involves patterning an electrically conductive layer to form metal lines on which is deposited an anisotropic plasma oxide (APO) resulting in a thin oxide on the sidewalls of the metal lines and a much thicker oxide on top of the lines. A low dielectric constant (k) polymer is deposited and the polymer and APO are chem/mech polished back to the top of the metal lines. A fluorine-doped silicon oxide (FSG) is deposited, and via holes are etched to provide electrical connections for the next level of interconnections. The APO provides wider openings between metal lines filled with the low k dielectric polymer thereby reducing the RC time delay of the circuit. The thick top APO provides more processing latitude for polishing back the APO and low k polymer. The FSG provides a lower dielectric constant k for further reducing the RC delay and a better thermal conductivity constant K for minimizing the Joule heating when the circuit is powered up. The process can be repeated several times to form a planar multilevel interconnection for completing wiring on the integrated circuit.

대표청구항 ▼

[ What is claimed is:] [1.] A method for fabricating multilevel metal interconnections having low dielectric constant insulators on a substrate comprising the steps of:a. providing a semiconductor substrate having semiconductor devices having contacts protected by a barrier layer;b. depositing a fir

[ What is claimed is:] [1.] A method for fabricating multilevel metal interconnections having low dielectric constant insulators on a substrate comprising the steps of:a. providing a semiconductor substrate having semiconductor devices having contacts protected by a barrier layer;b. depositing a first conductive layer for-contacting regions of said devices;c. patterning said first conductive layer to form interconnections for said devices;d. depositing an anisotropic plasma oxide over said patterned first conductive layer, said anisotropic plasma oxide being thicker on the top surface than on the sidewalls of said patterned conductive layer;e. depositing a low dielectric constant insulator on said anisotropic plasma oxide;f. planarizing said low dielectric constant insulator down to and further planarizing into said anisotropic plasma oxide by chemical/mechanical polishing to said top surface of said patterned first conductive layer;g. depositing a fluorine-doped oxide on said low dielectric insulator on said patterned first conductive layer;h. forming via holes in said fluorine-doped oxide to said patterned first conductive layer;i. depositing a second conductive layer on said fluorine-doped oxide and in said via holes;j. patterning said second conductive layer to form a second level of metal interconnections.