초록 ▼

A digital data handling system handling display signal streams has a video processor which is capable of high performance due to vector processing and special addressing modes. The video processor is a single VLSI device having a plurality of processors, each of which has associated instruction and

A digital data handling system handling display signal streams has a video processor which is capable of high performance due to vector processing and special addressing modes. The video processor is a single VLSI device having a plurality of processors, each of which has associated instruction and data caches, which are joined together by a wide data bus formed on the same substrate as the processors. Most audio and/or video compression algorithms use a Huffman style bit compression scheme with compression codes in variable length bit fields. The compressed data is a compacted bit stream which must be interpreted serially in order to extract the codes. In contrast to most microprocessors which process bit streams only inefficiently, the present invention uses a serialization FIFO to provide a hardware assist to the Huffman encoding/decoding.

대표청구항 ▼

[ What is claimed is:] [1.] An integrated circuit device comprising:a substrate,a plurality of identical processors formed on said substrate,each of said processors having an instruction cache, a data cache, a bus interface unit, and an arithmetic logic unit;a line bus formed on said substrate and i

[ What is claimed is:] [1.] An integrated circuit device comprising:a substrate,a plurality of identical processors formed on said substrate,each of said processors having an instruction cache, a data cache, a bus interface unit, and an arithmetic logic unit;a line bus formed on said substrate and interconnecting all of said plurality of processors for transferring data bit streams thereamong;a video input interface unit formed on said substrate and connected to said line bus for receiving an input signal stream;a video output interface unit formed on said substrate and connected to said line bus for delivering from the integrated circuit device an output video signal stream determined from processing by said plurality of processors;a host interface unit formed on said substrate and connected to said line bus for exchanging with a host processor control signals effective for governing the function of said plurality of processors;a control bus formed on said substrate and interconnecting said host interface unit and said plurality of processors for exchange of control and data signals therewith apart from data bit streams transferred over said line bus;a memory interface unit formed on said substrate and connected to said line bus for exchanging with memory elements data bit streams processed and to be processed by said plurality of processors;a serialization circuit interposed between said control bus and one of said processors for receiving and delivering data streams transferred with said control bus in parallel, fixed bit width transfers, for shifting the positions of bits in the data streams, and for transferring serial bit streams of varying length with said one of said processors.