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Auxiliary translation lookaside buffer for assisting in accessing data in remote address spaces

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-012/10
출원번호 US-0669979 (1996-06-25)
발명자 / 주소
  • Vishin Sanjay
  • Aybay Gunes
출원인 / 주소
  • Sun Microsystems, Inc.
대리인 / 주소
    Williams
인용정보 피인용 횟수 : 81  인용 특허 : 8

초록

A computer system includes a data processor, a primary translation lookaside buffer for storing page table entries and translating virtual addresses into physical addresses, local memory coupled to the data processor for storing data and computer programs at specified physical addresses, and remotel

대표청구항

[ What is claimed is:] [1.] A remote translation lookaside buffer, for use in a computer system having a data processor, a primary translation lookaside buffer for storing page table entries and converting virtual addresses into local physical addresses, local memory coupled to the data processor fo

이 특허에 인용된 특허 (8)

  1. Hayes Norman M. (Sunnyvale CA) Sindhu Pradeep (Mountain View CA) Frailong Jean-Marc (Palo Alto CA) Nanda Sunil (Los Altos CA), Broadcast demap for deallocating memory pages in a multiprocessor system.
  2. Hagersten Erik ; Zak ; Jr. Robert C., Hybrid NUMA COMA caching system and methods for selecting between the caching modes.
  3. Parrish Osey C. (Lauderdale Lakes FL) Peiffer ; Jr. Robert E. (Plantation FL) Thomas James H. (Plantation FL) Hilpert ; Jr. Edwin J. (Greenbelt MD), Memory address mechanism in a distributed memory architecture.
  4. Zolnowsky John E. (Austin TX) Whittington Charles L. (Buda TX) Keshlear William M. (Austin TX), Memory management unit.
  5. Sindhu Pradeep S. (Mountain View CA), Multiple address space system including address translator for receiving virtual addresses from bus and providing real a.
  6. Yamazaki Takeshi (Tokyo JPX), Multiprocessor system for locally managing address translation table.
  7. Casamatta Angelo (Cornaredo ITX) Mantellina Calogero (Cerro Maggiore ITX) Zanzottera Daniele (Busto Garolfo ITX), Multiprocessor system with global data replication and two levels of address translation units.
  8. Tetrick R. Scott (Portland OR), Use of deferred bus access for address translation in a shared memory clustered computer system.

이 특허를 인용한 특허 (81)

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