초록 ▼

A method and apparatus for identifying gated clocks within a circuit design. In a typical design, each of the number of gated clock signals is uniquely determined by a particular logical combination of a number of raw clock signals and a number of enable signals. In the present invention, the gated

A method and apparatus for identifying gated clocks within a circuit design. In a typical design, each of the number of gated clock signals is uniquely determined by a particular logical combination of a number of raw clock signals and a number of enable signals. In the present invention, the gated clock signals may be identified by: identifying which of the number of raw clock signals is coupled, through combinational logic, to a selected one of the number of state devices, thereby resulting in an identified raw clock signal; identifying which of the number of enable signals is coupled, through combinational logic, to the selected one of the number of state devices, thereby resulting in an identified enable signal; and determining which of the number of gated clock signals is uniquely determined by the particular combination of the identified raw clock signal and the identified enable signal.

대표청구항 ▼

[ What is claimed is:] [1.] Apparatus for identifying gated clocks in a circuit design, wherein the circuit design has a number of state devices, the circuit design includes a number of first signals and a number of second signals wherein selected ones of the number of first signals and selected one

[ What is claimed is:] [1.] Apparatus for identifying gated clocks in a circuit design, wherein the circuit design has a number of state devices, the circuit design includes a number of first signals and a number of second signals wherein selected ones of the number of first signals and selected ones of the number of second signals are logically combined, via combinational logic, to provide a number of gated clock signals, each of the number of gated clock signals is uniquely identified by the particular logical combination of the number of first and second signals, selected ones of the number of state devices receiving at least one of the number of gated clock signals, the improvement comprising:a. first identifying means for identifying which of the number of state devices are coupled, via the circuit design, to a first one of the number of first signals, thereby resulting in a number of first identified state devices;b. second identifying means for identifying which of the number of state devices are coupled, via the circuit design, to a first one of the number of second signals, thereby resulting in a number of second identified state devices;c. determining means coupled to said first and second identifying means for determining if any of the number of first identified state devices are the same state devices as the number of second identified state devices, and if so, identifying those as common state devices; andd. associating means coupled to said determining means for associating the particular gated clock signal that is uniquely identified by the particular logical combination of the first one of the number of first signals and the first one of the number of second signals with each of the common state devices.