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Hexagonal sense cell architecture 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-027/10
출원번호 US-0517189 (1995-08-21)
발명자 / 주소
  • Rostoker Michael D.
  • Koford James S.
  • Scepanovic Ranko
  • Jones Edwin R.
  • Padmanahben Gobi R.
  • Kapoor Ashok K.
  • Kudryavtsev Valerity B.,RUX
  • Andreev Alexander E.,RUX
  • Aleshin Stanislav V.,RUX
출원인 / 주소
  • LSI Logic Corporation
대리인 / 주소
    Mitchell, Silberberg & Knupp LLP
인용정보 피인용 횟수 : 81  인용 특허 : 13

초록

Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shap

대표청구항

[ What is claimed is:] [1.] A sense cell, comprising:a triangular structure fabricated on a semiconductor substrate;a first transistor formed as part of the triangular structure, the first transistor having a source region formed at one coner of the triangular structure, the source region of the fir

이 특허에 인용된 특허 (13)

  1. Modarres Hossein (Mountain View CA) Raam Susan (Fremont CA) Lai Jiun-Hao (Santa Clara CA), Hierarchical floorplanner.
  2. Hynecek Jaroslav (Richardson TX), Low 1/f noise amplifier for CCD imagers.
  3. Rosotker Michael D. (San Jose CA), Method of increasing the layout efficiency of dies on a wafer, and increasing the ratio of I/O area to active area per d.
  4. Yee Abraham (Santa Clara CA) Yeh Stanley (Fremont CA) Carmichael Tim (San Jose CA) Padmanabhan Gobi (Sunnyvale CA), Method of making integrated circuit structure with programmable conductive electrode/interconnect material.
  5. Dangelo Carlos (San Jose CA) Nagasamy Vijay K. (Mountain View CA) Bootehsaz Ahsan (Santa Clara CA) Rajan Sreeranga P. (Sunnyvale CA), Methodology for deriving executable low-level structural descriptions and valid physical implementations of circuits and.
  6. Rostoker Michael D. (Boulder Creek CA) Koford James S. (Mountain View CA) Scepanovic Ranko (San Jose CA) Jones Edwin R. (Sunnyvale CA) Padmanahben Gobi R. (Sunnyvale CA) Kapoor Ashok K. (Palo Alto CA, Microelectronic integrated circuit including triangular CMOS “nand”gate device.
  7. Rostoker Michael D. (Boulder Creek CA) Koford James S. (Mountain View CA) Scepanovic Ranko (San Jose CA) Jones Edwin R. (Sunnyvale CA) Padmanahben Gobi R. (Sunnyvale CA) Kapoor Ashok K. (Palo Alto CA, Microelectronic integrated circuit including triangular semiconductor “or”gate device.
  8. Rostoker Michael D. (San Jose CA), Multi-chip semiconductor arrangements using flip chip dies.
  9. Lidow Alexander (Manhattan Beach CA) Herman Thomas (Redondo Beach CA) Rumennik Vladimir (El Segundo CA), Plural polygon source pattern for mosfet.
  10. Neilson John M. S. (Norristown PA) Jones Frederick P. (Mountaintop PA) Yedinak Joseph A. (Wilkes-Barre PA) Rexer Christopher L. (Mountaintop PA), Power FET with gate segments covering drain regions disposed in a hexagonal pattern.
  11. Klodzinski Stanley J. (White Haven PA) Ronan ; Jr. Harold R. (Mountaintop PA) Neilson John M. S. (Norristown PA) Wheatley ; Jr. Carl F. (Drums PA), Power MOSFET.
  12. Rosotker Michael D. (San Jose CA), Semiconductor packaging technique yielding increased inner lead count for a given die-receiving area.
  13. Rostoker Michael D. (San Jose CA), Technique of increasing bond pad density on a semiconductor die.

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  2. Langhammer, Martin; Nguyen, Triet M.; Lin, Yi-Wen, Adder-rounder circuitry for specialized processing block in programmable logic device.
  3. Hoffberg, Steven M.; Hoffberg-Borghesani, Linda I., Alarm system controller and a method for controlling an alarm system.
  4. Langhammer, Martin, Angular range reduction in an integrated circuit device.
  5. Vora, Madhukar B., Apparatus and methods for high-density chip connectivity.
  6. Kaptanoglu, Sinan, Architecture for routing resources in a field programmable gate array.
  7. Kaptanoglu,Sinan, Architecture for routing resources in a field programmable gate array.
  8. Langhammer, Martin, Calculation of trigonometric functions in an integrated circuit device.
  9. Langhammer, Martin, Calculation of trigonometric functions in an integrated circuit device.
  10. Langhammer, Martin, Calculation of trigonometric functions in an integrated circuit device.
  11. Langhammer, Martin, Calculation of trigonometric functions in an integrated circuit device.
  12. Langhammer, Martin, Combined adder and pre-adder for high-radix multiplier circuit.
  13. Langhammer, Martin, Combined floating point adder and subtractor.
  14. Mauer, Volker, Combined interpolation and decimation filter for programmable logic device.
  15. Langhammer, Martin, Computing floating-point polynomials in an integrated circuit device.
  16. Langhammer, Martin; Pasca, Bogdan, Computing floating-point polynomials in an integrated circuit device.
  17. Langhammer, Martin, Configuring a programmable integrated circuit device to perform matrix multiplication.
  18. Langhammer, Martin, Configuring floating point operations in a programmable device.
  19. Langhammer, Martin, Configuring floating point operations in a programmable logic device.
  20. Leung, Wai-Bor; Lui, Henry Y., DSP block for implementing large multiplier on a programmable integrated circuit device.
  21. Langhammer,Martin; Starr,Gregory; Hwang,Chiao Kai, Devices and methods with programmable logic and digital signal processing regions.
  22. Langhammer,Martin; Starr,Gregory; Hwang,Chiao Kai, Devices and methods with programmable logic and digital signal processing regions.
  23. Demirsoy, Suleyman Sirri; Yi, Hyun, Digital signal processing circuit blocks with support for systolic finite-impulse-response digital filtering.
  24. Demirsoy, Suleyman Sirri; Yi, Hyun, Digital signal processing circuit blocks with support for systolic finite-impulse-response digital filtering.
  25. Demirsoy, Suleyman; Yi, Hyun, Digital signal processing circuit blocks with support for systolic finite-impulse-response digital filtering.
  26. Langhammer, Martin, Digital signal processing circuitry with redundancy and ability to support larger multipliers.
  27. Langhammer, Martin; Lin, Yi-Wen; Streicher, Keone, Digital signal processing circuitry with redundancy and bidirectional data paths.
  28. Langhammer, Martin, Discrete Fourier Transform in an integrated circuit device.
  29. Langhammer, Martin, Double-clocked specialized processing block in an integrated circuit device.
  30. Goodman, Rodney M., Electronic techniques for analyte detection.
  31. Goodman, Rodney M.; Koosh, Vincent; Dickson, Jeffrey, Electronic techniques for analyte detection.
  32. Brazier, Stephen William Cruwys, Geometrical shape apparatus.
  33. Shively, John, Hexadecagonal routing.
  34. Chou, Shin-I, High-rate interpolation or decimation filter in integrated circuit device.
  35. Langhammer, Martin, Implementing division in a programmable integrated circuit device.
  36. Langhammer, Martin, Implementing large multipliers in a programmable integrated circuit device.
  37. Langhammer, Martin, Implementing mixed-precision floating-point operations in a programmable integrated circuit device.
  38. Langhammer, Martin, Implementing multipliers in a programmable integrated circuit device.
  39. Hoffberg, Steven M.; Hoffberg-Borghesani, Linda I., Internet appliance system and method.
  40. Langhammer, Martin; Tharmalingam, Kumara, Large multiplier for programmable logic device.
  41. Langhammer, Martin; Tharmalingam, Kumara, Large multiplier for programmable logic device.
  42. Langhammer, Martin; Tharmalingam, Kumara, Large multiplier for programmable logic device.
  43. Langhammer, Martin; Tharmalingam, Kumara, Large multiplier for programmable logic device.
  44. Langhammer, Martin, Matrix decomposition in an integrated circuit device.
  45. Kurtz, Brian L., Matrix operations in an integrated circuit device.
  46. Langhammer, Martin, Matrix operations in an integrated circuit device.
  47. Pell, III, Edwin A., Method and apparatus for improving resolution of objects in a semiconductor wafer.
  48. Pell, III, Edwin A., Method and apparatus for improving resolution of objects in a semiconductor wafer.
  49. Mauer, Volker; Demirsoy, Suleyman Sirri, Method for configuring a finite impulse response filter in a programmable logic device.
  50. Vora, Madhukar B., Methods and apparatus for high-density chip connectivity.
  51. Streicher, Keone; Langhammer, Martin; Lin, Yi-Wen; Leung, Wai-Bor; Lewis, David; Mauer, Volker; Lui, Henry Y.; Demirsoy, Suleyman Sirri; Yi, Hyun, Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry.
  52. Streicher, Keone; Langhammer, Martin; Lin, Yi-Wen; Leung, Wai-Bor; Lewis, David; Mauer, Volker; Lui, Henry Y.; Demirsoy, Suleyman Sirri; Yi, Hyun, Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry.
  53. Streicher, Keone; Langhammer, Martin; Lin, Yi-Wen; Leung, Wai-Bor; Lewis, David; Mauer, Volker; Lui, Henry Y.; Demirsoy, Suleyman Sirri; Yi, Hyun, Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry.
  54. Langhammer, Martin, Multi-operand floating point operations in a programmable integrated circuit device.
  55. Langhammer, Martin, Multiple-precision processing block in a programmable integrated circuit device.
  56. Choe, Kok Heng; Ngai, Tony K; Lui, Henry Y., Multiplier-accumulator circuitry and methods.
  57. Langhammer, Martin, Normalization of floating point operations in a programmable integrated circuit device.
  58. Langhammer, Martin, Normalization of floating point operations in a programmable integrated circuit device.
  59. Mauer, Volker; Langhammer, Martin, Pipelined systolic finite impulse response filter.
  60. Langhammer, Martin, Polynomial calculations optimized for programmable integrated circuit device structures.
  61. Yamada, Naoki, Power semiconductor chip, power semiconductor module, inverter apparatus, and inverter-integrated motor.
  62. Langhammer, Martin, Programmable device using fixed and configurable logic to implement floating-point rounding.
  63. Langhammer, Martin, Programmable device using fixed and configurable logic to implement recursive trees.
  64. Mauer, Volker; Langhammer, Martin, Programmable device with specialized multiplier blocks.
  65. Langhammer, Martin, QR decomposition in an integrated circuit device.
  66. Mauer, Volker, QR decomposition in an integrated circuit device.
  67. Lee, Hui Yu; Kuo, Feng Wei; Kuan, Jui-Feng; Cheng, Yi-Kan, Semiconductor structure.
  68. Lee, Hui Yu; Kuo, Feng Wei; Kuan, Jui-Feng; Cheng, Yi-Kan, Semiconductor structure and method of generating masks for making integrated circuit.
  69. Lee, Hui Yu; Kuo, Feng Wei; Kuan, Jui-Feng; Cheng, Yi-Kan, Semiconductor structure having a plurality of conductive paths.
  70. Langhammer, Martin; Dhanoa, Kulwinder, Solving linear matrices in an integrated circuit device.
  71. Langhammer, Martin, Specialized processing block for implementing floating-point multiplier with subnormal operation support.
  72. Xu, Lei; Mauer, Volker; Perry, Steven, Specialized processing block for programmable integrated circuit device.
  73. Langhammer, Martin; Lee, Kwan Yee Martin; Azgomi, Orang; Streicher, Keone; Lin, Yi-Wen, Specialized processing block for programmable logic device.
  74. Langhammer, Martin; Lee, Kwan Yee Martin; Azgomi, Orang; Streicher, Keone; Pelt, Robert L., Specialized processing block for programmable logic device.
  75. Langhammer, Martin; Lee, Kwan Yee Martin; Nguyen, Triet M.; Streicher, Keone; Azgomi, Orang, Specialized processing block for programmable logic device.
  76. Lee, Kwan Yee Martin; Langhammer, Martin; Lin, Yi-Wen; Nguyen, Triet M., Specialized processing block for programmable logic device.
  77. Lee, Kwan Yee Martin; Langhammer, Martin; Nguyen, Triet M.; Lin, Yi-Wen, Specialized processing block for programmable logic device.
  78. Langhammer, Martin, Specialized processing block with fixed- and floating-point structures.
  79. Kaptanoglu, Sinan, Turn architecture for routing resources in a field programmable gate array.
  80. Roy,Rini, Vehicle control system having an adaptive controller.
  81. Cline Ronald L., Very fine-grain field programmable gate array architecture and circuitry.
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