초록 ▼

Methods of planarizing one or more layers having an irregular top surface topology in a semiconductor device based on an underlying MOS structure are disclosed. Methods of creating doped wells or regions for the underlying MOS structure are also disclosed, using thick oxide growths on the surface of

Methods of planarizing one or more layers having an irregular top surface topology in a semiconductor device based on an underlying MOS structure are disclosed. Methods of creating doped wells or regions for the underlying MOS structure are also disclosed, using thick oxide growths on the surface of the substrate to mask implantation of ions into the wells. A technique for creating a pair of adjacent complementary oppositely-doped wells, such as for a CMOS structure, using a thick oxide growths as a mask is also disclosed. One of the methods of planarizing the one or more layers involves depositing, densifying and re-flowing a layer of glass on top of the topological layer. Another method of planarizing the one or more layers involves depositing, densifying and chemical-mechanically polishing the deposited and densified glass, thereby avoiding an additional temperature cycle (i.e., for re-flowing the glass) which would adversely affect underlying diffusions.

대표청구항 ▼

[ What is claimed is:] [1.] A method of fabricating a semiconductor device, comprising:providing a precursor CMOS semiconductor substrate having a plurality of interleaved complementary first and second well regions formed in said substrate and overlaid by a plurality of stacked silicon dioxide laye

[ What is claimed is:] [1.] A method of fabricating a semiconductor device, comprising:providing a precursor CMOS semiconductor substrate having a plurality of interleaved complementary first and second well regions formed in said substrate and overlaid by a plurality of stacked silicon dioxide layers including a first layer, a second layer and a third layer;each individual first well region and second well region having a source region and a drain region spaced from one another and on opposite sides of a gate element centered over its respective well;forming first vias through said first layer, said second layer, and said third layer at about each respective one of the source regions and drain regions;forming metal plugs in the first vias to contact individual ones of the source regions and the drain regions respectively;forming another plurality of stacked silicon dioxide layers on the substrate in the last mentioned forming step, said another plurality of silicon dioxide layers including a fourth layer and a fifth layer;forming second vias through said fourth layer and said fifth layer;applying a barrier metal layer over said fifth layer to fill the second vias;applying a metal filler over the barrier metal layer;applying a metal cap over said metal filler; andapplying a passivation layer over said metal cap and said fifth layer.