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Embedded power and ground plane structure 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
출원번호 US-0873102 (1997-06-11)
발명자 / 주소
  • Bhattacharyya Arup
  • Leidy Robert K.
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Ratner & PrestiaShkurko
인용정보 피인용 횟수 : 32  인용 특허 : 14

초록 ▼

A device architecture with embedded planar conductive ground and power planes in the device architecture. The apparatus includes a first conductive plane, a second conductive plane, a signal plane disposed between the first and second conductive planes, and a logic level disposed adjacent the first

대표청구항 ▼

[ What is claimed:] [1.] An apparatus comprising:a first conductive plane;a second conductive plane;a signal plane disposed between the first and second conductive planes; anda logic level disposed adjacent the first conductive plane and connected to the signal plane through at least one via in the

이 특허에 인용된 특허 (14)

  1. Vu Quat T. (Santa Clara CA) Gardner Donald S. (Mountain View CA), Capacitor fabricated on a substrate containing electronic circuitry.
    상세보기
  2. Gebara Ghassan R. (Spring TX), Electromagnetic radiation reduction technique using grounded conductive traces circumscribing internal planes of printed.
    상세보기
  3. Matsumoto Ryoichi (Tokyo JPX) Kuroda Toshikazu (Tokyo JPX) Kato Takao (Tokyo JPX), Fabrication process for wafer alignment marks by using peripheral etching to form grooves.
    상세보기
  4. Thomas Michael E. (Cupertino CA) Chinn Jeffrey D. (Foster City CA), High performance interconnect system for an integrated circuit.
    상세보기
  5. Allen David H. (Boise ID), Method for forming a shielding structure for decoupling signal traces in a semiconductor.
    상세보기
  6. Thomas Michael E. (Cupertino CA) Chinn Jeffrey D. (Foster City CA), Method of fabricating a high performance interconnect system for an integrated circuit.
    상세보기
  7. Ishibashi Takeo (Hyogo JPX), Method of forming a pattern of a multilayer type semiconductor device.
    상세보기
  8. Boyle Steven R. (Santa Clara CA) Proebsting Robert J. (Los Altos Hills CA) Herndon William H. (Sunnyvale CA), Method of making a multi-layer to package.
    상세보기
  9. Smith W. David (Abington CT) Olenick John A. (Thompson CT) Barton Carlos L. (Brooklyn CT) Cercena Jane L. (Ashford CT) Navarro Daniel J. (Putnam CT) Olenick Kathleen R. (Thompson CT) Kneeland Angela , Method of manufacture multichip module substrate.
    상세보기
  10. Oppenberg George A. (Brooklyn NY), Multilayer printed circuit board with pseudo-coaxial transmission lines.
    상세보기
  11. Sun Shih-Wei (Austin TX) Kosa Yasunobu (Austin TX) Yeargain John R. (Austin TX), Process for forming a structure which electrically shields conductors.
    상세보기
  12. Saito Yasuyuki (Yokohama JPX), Semiconductor integrated circuit having a long bus line.
    상세보기
  13. Jost Mark E. (Boise ID) Hansen David J. (Boise ID) McDonald Steven M. (Meridian ID), Semiconductor wafer, wafer alignment patterns and method of forming wafer alignment patterns.
    상세보기
  14. Wheeler Richard L. (San Jose CA), Special interconnect layer employing offset trace layout for advanced multi-chip module packages.
    상세보기

이 특허를 인용한 특허 (32)

  1. Diewald, Wolfgang; Mümmler, Klaus, Application of alignment marks to wafer.
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  2. Carroll Michael Scott ; Ivanov Tony Georgiev ; Martin Samuel Suresh, Article for de-embedding parasitics in integrated circuits.
    상세보기
  3. Anthony Grass, Capacitor for a semiconductor device.
    상세보기
  4. Satya, Akella V. S.; Mantalas, Lynda C.; Pinto, Gustavo A., Chemical mechanical polishing test structures and methods for inspecting the same.
    상세보기
  5. Satya,Akella V. S.; Mantalas,Lynda C.; Pinto,Gustavo A., Chemical mechanical polishing test structures and methods for inspecting the same.
    상세보기
  6. Kerry Bernstein ; Robert M. Geffken ; Anthony K. Stamper ; Stephen A. St. Onge, Damascene metal capacitor.
    상세보기
  7. Zelikson, Michael; Waizman, Alex, Embedded power gating.
    상세보기
  8. Arai, Toshiyuki; Kawai, Ryousei; Tsuchiyama, Hirofumi; Kanai, Fumiyuki; Nakabayashi, Shinichi, Fabrication method of semiconductor integrated circuit device.
    상세보기
  9. Arai, Toshiyuki; Kawai, Ryousei; Tsuchiyama, Hirofumi; Kanai, Fumiyuki; Nakabayashi, Shinichi, Fabrication method of semiconductor integrated circuit device.
    상세보기
  10. Arai, Toshiyuki; Kawai, Ryousei; Tsuchiyama, Hirofumi; Kanai, Fumiyuki; Nakabayashi, Shinichi, Fabrication method of semiconductor integrated circuit device.
    상세보기
  11. Arai,Toshiyuki; Kawai,Ryousei; Tsuchiyama,Hirofumi; Kanai,Fumiyuki; Nakabayashi,Shinichi, Fabrication method of semiconductor integrated circuit device.
    상세보기
  12. Carroll Michael Scott ; Ivanov Tony Georgiev ; Martin Samuel Suresh, Integrated circuit comprising means for high frequency signal transmission.
    상세보기
  13. Awaya,Nobuyoshi, Manufacturing method for short distance wiring layers and long distance wiring layers in a semiconductor device.
    상세보기
  14. Jonathan Chapple-Sokol ; Paul M. Feeney ; Robert M. Geffken ; David V. Horak ; Mark P. Murray ; Anthony K. Stamper, Metallurgy for semiconductor devices.
    상세보기
  15. Ying-Ho Chen TW; Wen-Chih Chiou TW; Tsu Shih TW; Syun-Ming Jang TW, Method to eliminate copper CMP residue of an alignment mark for damascene processes.
    상세보기
  16. Cheong, Seong-Hwee; Choi, Gil-Heyun; Lee, Sang-Woo; Park, Jin-Ho, Methods of fabricating semiconductor devices including contact plugs having laterally extending portions.
    상세보기
  17. Pinto, Gustavo A.; Leslie, Brian C.; Adler, David L.; Satya, Akella V. S.; Satya, legal representative, Padma A.; Long, Robert Thomas; Walker, David J., Multiple directional scans of test structures on semiconductor integrated circuits.
    상세보기
  18. Archibald J. Allen ; Orest Bula ; John M. Cohn ; Daniel Cole ; Edward W. Conrad ; William C. Leipold, Optical Proximity Correction Structures Having Decoupling Capacitors.
    상세보기
  19. Hamada, Koji, Semiconductor device with interlayer film comprising a diffusion prevention layer to keep metal impurities from invading the underlying semiconductor substrate.
    상세보기
  20. Chen, Shao-Yun; Chen, Hsien-Wei; Huang, Li-Hsien, Test key strcutures, integrated circuit packages and methods of forming the same.
    상세보기
  21. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  22. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  23. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  24. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  25. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  26. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  27. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  28. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  29. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  30. Lin,Mou Shiung, Top layers of metal for high performance IC's.
    상세보기
  31. Lin Yung-Fa,TWX, Vertical via/contact.
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  32. Zhang,Guobiao, nF-Opening Aiv Structures.
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