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Semiconductor device with improved adhesion between titanium-based metal wiring layer and insulation film 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/522
출원번호 US-0969647 (1997-11-13)
우선권정보 JP-0085989 (1995-03-20)
발명자 / 주소
  • Matsuno Tadashi,JPX
출원인 / 주소
  • Kabushiki Kaisha Toshiba, JPX
대리인 / 주소
    Loeb & Loeb LLP
인용정보 피인용 횟수 : 46  인용 특허 : 2

초록

A semiconductor device includes a substrate, an insulation film formed above the substrate and containing silicon-fluorine bonds, and a titanium-based metal wiring layer formed on the insulation film, the titanium-based metal wiring layer containing fluorine which is diffused from the insulation fil

대표청구항

[ What is claimed is:] [1.] A semiconductor device, comprising:a substrate having a first and a second region;a first insulating film formed above said substrate and containing silicon-fluorine bonds, said first insulating film having a first thickness on said first region and having a second thickn

이 특허에 인용된 특허 (2)

  1. Homma Tetsuya (Tokyo JPX), Method for fabricating a semiconductor device having a multi-layered interconnection structure.
  2. Kondo Toshihiko (Suwa JPX) Tanaka Kazuo (Suwa JPX) Yasuda Hirofumi (Suwa JPX), Semiconductor device having an inter-layer insulating film disposed between two wiring layers.

이 특허를 인용한 특허 (46)

  1. Aaron Schoenfeld ; Rajesh Somasekharan, Integrated circuit having conductive paths of different heights formed from the same layer structure and method for forming the same.
  2. Schoenfeld, Aaron; Somasekharan, Rajesh, Integrated circuit having conductive paths of different heights formed from the same layer structure and method for forming the same.
  3. Izumi Katsuya,JPX, Interconnect structure of semiconductor device.
  4. Dawson Robert, Metal layer interconnects with improved performance characteristics.
  5. Maex, Karen; Baklanov, Mikhail Rodionovich; Vanhaelemeersch, Serge, Metallization structure on a fluorine-containing dielectric and a method for fabrication thereof.
  6. Jeng-Jie Peng TW; Ming-Dou Ker TW; Nien-Ming Wang TW, Method for improving integrated circuits bonding firmness.
  7. Peng, Jeng-Jie; Ker, Ming-Dou; Wang, Nien-Ming, Method for improving integrated circuits bonding firmness.
  8. Yabu Toshiki,JPX ; Segawa Mizuki,JPX, Method of making a semiconductor device.
  9. Tomita Kazuo,JPX, Method of manufacturing a semiconductor device with a stacked via.
  10. Yokoyama Takashi,JPX ; Yamada Yoshiaki,JPX ; Kishimoto Koji,JPX, Multilevel interconnecting structure in semiconductor device and method of forming the same.
  11. Yoo Chue-San,TWX, Planarization process using tailored etchback and CMP.
  12. Hayashi, Eiji; Go, Kyo; Harada, Kozo; Baba, Shinji, Semiconductor device.
  13. Tasaka, Kazuhiro, Semiconductor device.
  14. Hayashi, Eiji; Go, Kyo; Harada, Kozo; Baba, Shinji, Semiconductor device and method of manufacturing.
  15. Hayashi, Eiji; Go, Kyo; Harada, Kozo; Baba, Shinji, Semiconductor device and method of manufacturing the same.
  16. Hayashi, Eiji; Go, Kyo; Harada, Kozo; Baba, Shinji, Semiconductor device and method of manufacturing the same.
  17. Hayashi, Eiji; Go, Kyo; Harada, Kozo; Baba, Shinji, Semiconductor device and method of manufacturing the same.
  18. Hayashi, Eiji; Go, Kyo; Harada, Kozo; Baba, Shinji, Semiconductor device and method of manufacturing the same.
  19. Hayashi, Eiji; Go, Kyo; Harada, Kozo; Baba, Shinji, Semiconductor device and method of manufacturing the same.
  20. Hayashi, Eiji; Go, Kyo; Harada, Kozo; Baba, Shinji, Semiconductor device and method of manufacturing the same.
  21. Hayashi, Eiji; Go, Kyo; Harada, Kozo; Baba, Shinji, Semiconductor device and method of manufacturing the same.
  22. Tomita Kazuo,JPX, Semiconductor device and method of manufacturing the same.
  23. Koyanagi Kenichi,JPX ; Fujii Kunihiro,JPX ; Usami Tatsuya,JPX ; Kishimoto Koji,JPX, Semiconductor device and process for production thereof.
  24. Yabu Toshiki,JPX ; Segawa Mizuki,JPX, Semiconductor interconnect formed over an insulation and having moisture resistant material.
  25. Yabu, Toshiki; Segawa, Mizuki, Semiconductor interconnect formed over an insulation and having moisture resistant material.
  26. Yabu,Toshiki; Segawa,Mizuki, Semiconductor interconnect formed over an insulation and having moisture resistant material.
  27. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  28. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  29. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  30. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  31. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  32. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  33. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  34. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  35. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  36. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  37. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  38. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  39. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  40. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  41. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  42. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  43. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  44. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  45. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  46. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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