초록 ▼

A field programmable gate array (FPGA) having a plurality of configurable logic blocks (CLBs). Each of the CLBs includes programmable interconnect resources, a field programmable configurable logic element (CLE) circuit and a corresponding non-field programmable gate array. The programmable intercon

A field programmable gate array (FPGA) having a plurality of configurable logic blocks (CLBs). Each of the CLBs includes programmable interconnect resources, a field programmable configurable logic element (CLE) circuit and a corresponding non-field programmable gate array. The programmable interconnect resources are programmed to selectively couple or decouple each CLE circuit from its corresponding non-field programmable gate array. Dedicated interconnect resources enable adjacent non-field programmable gate arrays to be coupled. By coupling adjacent non-field programmable gate arrays, one or more relatively large nonfield programmable gate arrays can be formed. The non-field programmable gate arrays have a greater logic density than the CLE circuits, thereby providing an improved logic density to the CLBs. Moveover, because each CLB includes a non-field programmable gate array, each of the CLE circuits is readily connectable to a non-field programmable gate array. The non-field programmable gate array can be used to provide a plurality of mask-programmable input/output driver circuits for connection to the pads of the FPGA.

대표청구항 ▼

[ What is claimed is:] [1.] A field programmable gate array (FPGA) formed in and on an integrated circuit substrate comprising a plurality of configurable logic blocks (CLBs), each comprising:interconnect lines for interconnecting said CLBs to each other,a field programmable configurable logic eleme

[ What is claimed is:] [1.] A field programmable gate array (FPGA) formed in and on an integrated circuit substrate comprising a plurality of configurable logic blocks (CLBs), each comprising:interconnect lines for interconnecting said CLBs to each other,a field programmable configurable logic element (CLE), anda non-field programmable gate array element, said non-field programmable gate array element comprising an application independent pattern of transistors formed within the substrate and application specific connectors formed above the substrate.