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Method of producing stepped wall interconnects and gates 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/3205
출원번호 US-0323262 (1994-10-14)
발명자 / 주소
  • Hata William Y.
출원인 / 주소
  • SGS-Thomson Microelectronics, Inc.
대리인 / 주소
    Galantha
인용정보 피인용 횟수 : 55  인용 특허 : 19

초록

A method is provided for making conductive structures whereby an insulating layer is formed over a substrate. A conductive layer is then formed over the insulating layer. A first photoresist layer is formed over the conductive layer, patterned and developed. The conductive layer is etched after whic

대표청구항

[ What is claimed is:] [1.] A method of producing a conductive structure of a semiconductor integrated circuit having stepped walls, comprising the steps of:forming an insulating layer over a substrate;forming a conductive layer over the insulating layer;forming a first photoresist layer over the co

이 특허에 인용된 특허 (19)

  1. Wang Chen-Chin (7880 Creekline Dr. Cupertino CA 95014) Hong Yeun-Ding G. (1686 Hadeock Ct. San Jose CA 95132) Chiao Stephen S. (20437 Kilbride Ct. Saratoga CA 95070), Contactless non-volatile memory array cells.
  2. Huang Tiao-Yuan (Cupertino CA), Double implanted LDD transistor self-aligned with gate.
  3. Satoh Shinichi (Hyogo JPX) Ozaki Hiroji (Hyogo JPX) Eimori Takahisa (Hyogo JPX), Field effect transistor with T-shaped gate electrode.
  4. Taniguchi Akihisa (Itami JPX), Field effect transistor with T-shaped gate electrode.
  5. Madan Sudhir K. (Dallas TX), Local interconnect for stacked polysilicon device.
  6. Inuishi Masahide (Hyogo JPX) Tsukamoto Katsuhiro (Hyogo JPX), MOS type field effect transistor having LDD structure.
  7. Tsubone Ko (Tokyo JPX), MOSFET fabrication process with lightly-doped drain using local oxidation step to pattern gate electrode.
  8. Fisher Duncan M. (Austin TX) Klein Jeffrey L. (Austin TX), Method for forming self-aligned vias in multi-level metal integrated circuits.
  9. Willer Josef (Riemerling DEX) Lefranc Guy (Munich DEX), Method for manufacturing an FET with asymmetrical gate region.
  10. Kakiuchi Takao (Takarazuka JPX), Method for patterning a metal layer.
  11. Chao Fung-Ching (Tainan Shih TWX), Method of fabricating a LDDFET with self-aligned silicide.
  12. Hirota Takatoshi (Kawasaki JPX), Method of reactive ion etching of a thin copper film.
  13. Miyakawa Tadashi (Tokyo JPX) Asano Masamichi (Tokyo JPX) Taura Tadayuki (Kawasaki JPX) Shoji Atsushi (Yokohama JPX) Inami Michiharu (Tama JPX), Nonvolatile semiconductor memory.
  14. Wu Andrew L. (Shrewsbury MA), Planar interconnect for integrated circuits.
  15. Vora Madhukar B. (Los Gatos CA), Process for making high performance CMOS and bipolar integrated devices on one substrate with reduced cell size.
  16. Azuma Kenichi (Tenri JPX) Kawamura Akio (Nara JPX), Process for manufacturing semiconductor device.
  17. Deslauriers Jean S. (Bromont NJ CAX) Levinstein Hyman J. (Berkeley Heights NJ), Reactive ion etching of tantalum and silicon.
  18. Satoh Shinichi (Hyogo JPX) Hirayama Makoto (Hyogo JPX) Nagatomo Masao (Hyogo JPX) Ogoh Ikuo (Hyogo JPX) Ohno Yoshikazu (Hyogo JPX) Fujinaga Masato (Hyogo JPX), Semiconductor device having interconnection layers of T-shape cross section.
  19. Young Peter L. (South Barrington IL) Cech Jay (Elmhurst IL) Li Kin (Lombard IL), Thin-film electrical connections for integrated circuits.

이 특허를 인용한 특허 (55)

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  2. Lindert, Nick; Cea, Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
  3. Doyle, Brian S.; Jin, Been-Yih; Kavalieros, Jack T.; Datta, Suman; Brask, Justin K.; Chau, Robert S., CMOS devices with a single work function gate electrode and method of fabrication.
  4. Roschak, Edmund J., Devices for delivering substances through an extra-anatomic opening created in an airway.
  5. Brask, Justin K.; Datta, Suman; Doczy, Mark L.; Blackwell, James M.; Metz, Matthew V.; Kavalieros, Jack T.; Chau, Robert S., Dielectric interface for group III-V semiconductor device.
  6. Radosavljevic, Marko; Datta, Suman; Doyle, Brian S.; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Majumdar, Amian; Chau, Robert S., Field effect transistor with metal source/drain regions.
  7. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  8. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  9. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  10. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
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  12. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  13. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  14. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  15. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors.
  16. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
  17. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
  18. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  19. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  20. Cho Gyung-Su,KRX, Method for making semiconductor device having via hole.
  21. Sasaki, Katsuhito, Method of fabricating LDMOS semiconductor devices.
  22. Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Chau, Robert S., Method of patterning a film.
  23. Hsiao, Hsi Mao, Method to improve borderless metal line process window for sub-micron designs.
  24. Keast, Thomas; Laufer, Michael D.; Wibowo, Henky; Cole, Cary; Kaplan, Gary S.; Roschak, Edmund J., Methods and devices for diagnosing, monitoring, or treating medical conditions through an opening through an airway wall.
  25. Brask, Justin K.; Kavalieros, Jack; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S.; Doyle, Brian S., Methods for patterning a semiconductor film.
  26. Rios, Rafael; Doyle, Brian S.; Linton, Jr., Thomas D.; Kavalieros, Jack, N-gate transistor.
  27. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
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  33. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  34. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
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  37. Brask, Justin K.; Dovle, Brian S.; Kavalleros, Jack; Doczy, Mark; Shah, Uday; Chau, Robert S., Nonplanar transistors with metal gate electrodes.
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  39. Kavalieros,Jack T.; Brask,Justin K.; Doyle,Brian S.; Shah,Uday; Datta,Suman; Doczy,Mark L.; Metz,Matthew V.; Chau,Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
  40. Gardner Mark I. ; Fulford H. Jim ; May Charles E., Process for making high performance MOSFET with scaled gate electrode thickness.
  41. Kanamori Jun,JPX, Semiconductor device and method of manufacturing the same.
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  47. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
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  50. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
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  52. Takehashi, Shin-itsu; Ikuta, Shigeo; Kawakita, Tetsuo; Inoue, Mayumi; Kuramasu, Keizaburo, Thin-film transistor, panel, and methods for producing them.
  53. Takehashi, Shin-itsu; Ikuta, Shigeo; Kawakita, Tetsuo; Inoue, Mayumi; Kuramasu, Keizaburo, Thin-film transistor, panel, and methods for producing them.
  54. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
  55. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
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