$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Pulsed domino latches 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03K-019/00
  • H03K-019/096
출원번호 US-0774261 (1996-12-27)
발명자 / 주소
  • Mehta Gaurav G.
  • Harris David
  • Singh S. Deo
출원인 / 주소
  • Intel Corporation
대리인 / 주소
    Blakely, Sokoloff, Taylor & Zafman LLP
인용정보 피인용 횟수 : 54  인용 특허 : 6

초록

The present invention is a novel method of interfacing static logic to domino logic. A static logic block is connected to one input of a domino evaluation tree. The domino evaluation tree operates only during a brief window of time, while an evaluation control block is ON. Since the input to the dom

대표청구항

[ What is claimed is:] [1.] An interface between a static logic block and a domino gate controlled by a clock signal, comprising:a domino evaluation tree having an input connected to an output of said static logic block; andan evaluation control block;said domino evaluation tree evaluating during a

이 특허에 인용된 특허 (6)

  1. Wu Chung-Yu (Hsinchu TWX) Cheng Kuo-Hsing (Taipei TWX), CMOS dynamic logic structure.
  2. Gupta Shantanu R. (Beaverton OR) Fletcher Thomas D. (Portland OR), Clocking scheme for latching of a domino output.
  3. Okano Yoshiaki (Tokyo JPX), Dynamic decoder circuit with charge-sharing prevention means.
  4. Iwamura Masahiro (Hitachi JPX) Hotta Takashi (Hitachi JPX) Maejima Hideo (Hitachi JPX), Dynamic logic circuit including bipolar transistors and field-effect transistors.
  5. Harris David (Santa Clara CA) Huang Sunny C. (Cupertino CA) Nadir James (San Jose CA) Chu Ching-Hua (San Jose CA) Stinson Jason C. (Mountain View CA) Ilkbahar Alper (Santa Cruz CA), Opportunistic time-borrowing domino logic.
  6. Sutherland Ivan E. (Santa Monica CA) Molnar Charles E. (Webster Grove MO), Three conductor asynchronous signaling.

이 특허를 인용한 특허 (54)

  1. Pitkethly, Scott; Masleid, Robert Paul, Advanced repeater utilizing signal distribution delay.
  2. Pitkethly, Scott, Advanced repeater with duty cycle adjustment.
  3. Pitkethly, Scott, Advanced repeater with duty cycle adjustment.
  4. Pitkethly, Scott, Advanced repeater with duty cycle adjustment.
  5. Thomas D. Fletcher, Apparatus, method and system for a controllable pulse clock delay arrangement to control functional race margins in a logic data path.
  6. Fletcher Thomas D., Apparatus, method and system for a logic arrangement having mutually exclusive outputs controlled by buffering cross-coupled devices.
  7. Thomas D. Fletcher, Apparatus, method and system for a ratioed NOR logic arrangement.
  8. Fletcher Thomas D., Apparatus, method and system for providing LVS enables together with LVS data.
  9. Paul D. Madland, Circuit to reduce charge sharing for domino circuits with pulsed clocks.
  10. Masleid, Robert Paul; Dholabhai, Vatsal, Circuit with enhanced mode and normal mode.
  11. Masleid, Robert Paul; Kowalczyk, Andre, Circuits and methods for detecting and assisting wire transitions.
  12. Masleid, Robert, Circuits, systems and methods relating to a dynamic dual domino ring oscillator.
  13. Masleid, Robert Paul, Column select multiplexer circuit for a domino random access memory array.
  14. Masleid, Robert Paul, Configurable delay chain with stacked inverter delay elements.
  15. Masleid, Robert Paul, Configurable delay chain with switching control for tail delay elements.
  16. Masleid, Robert Paul, Configurable tapered delay chain with multiple sizes of delay elements.
  17. Poirier Christopher Allan ; Naffziger Samuel D ; Kever Wayne Dervon, Contention based logic gate driving a latch and driven by pulsed clock.
  18. Masleid, Robert P.; Pitkethly, Scott, Cross point switch.
  19. Masleid, Robert P.; Pitkethly, Scott, Cross point switch.
  20. Masleid, Robert P.; Pitkethly, Scott, Cross point switch.
  21. Bourgin,Bernard, Dynamic phase assignment optimization using skewed static buffers in place of dynamic buffers.
  22. Masleid, Robert P, Dynamic ring oscillators.
  23. Chai, Chiaming; Ge, Shaoping; Liles, Stephen Edward; Shah, Chintan Hemendrakumar, Dynamic voltage level shifters employing pulse generation circuits, and related systems and methods.
  24. Lundberg, James R.; Qureshi, Imran, Fast dynamic register.
  25. Qureshi, Imran, Fast dynamic register with transparent latch.
  26. Milshtein, Mark S.; Sprague, Milo D.; Chappell, Terry I.; Fletcher, Thomas D., Global clock self-timed circuit with self-terminating precharge for high frequency applications.
  27. Masleid, Robert P, Inverting zipper repeater circuit.
  28. Masleid, Robert P., Inverting zipper repeater circuit.
  29. Masleid, Robert Paul, Inverting zipper repeater circuit.
  30. Masleid, Robert, Leakage efficient anti-glitch filter.
  31. Tzartzanis, Nestor; Walker, William W., Low-to-high voltage conversion method and system.
  32. Bourgin,Bernard, Method and apparatus for mixing static logic with domino logic.
  33. Lattimore, George McNeil; Mikan, Jr., Donald George; Paredes, Jose Angel; Yeung, Gus Wai-Yan, Method for skipping a latch in timing-sensitive dynamic circuits of a multi-clocked system with unspecific underlap requirement.
  34. Campbell,Brian J., Monotonic leakage-tolerant logic circuits.
  35. Masleid, Robert Paul, Power efficient multiplexer.
  36. Masleid, Robert Paul, Power efficient multiplexer.
  37. Masleid, Robert Paul, Power efficient multiplexer.
  38. Masleid, Robert Paul, Power efficient multiplexer.
  39. Gajendra P. Singh ; Joseph I. Chamdani, Pulse-based high speed flop circuit.
  40. Milo D. Sprague ; Rajesh Kumar ; Robert J. Murray, Pulsed circuit topology including a pulsed, domino flip-flop.
  41. Sprague, Milo D.; Li, David K.; Murray, Robert J., Pulsed circuit topology to perform a memory array write operation.
  42. Hsu, Steven K.; Lu, Shih-Lien L.; Krishnamurthy, Ram, Register files and caches with digital sub-threshold leakage current calibration.
  43. Masleid, Robert Paul; Dholabhai, Vatsal; Klingner, Christian, Repeater circuit having different operating and reset voltage ranges, and methods thereof.
  44. Masleid, Robert Paul; Dholabhai, Vatsal, Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability.
  45. Sprague, Milo D.; Murray, Robert J., Reset first latching mechanism for pulsed circuit topologies.
  46. Stoiber, Steven T.; Siu, Stuart, Ring based impedance control of an output driver.
  47. Stoiber, Steven T.; Siu, Stuart, Ring based impedance control of an output driver.
  48. Masleid, Robert Paul; Sousa, Jose; Kottapalli, Venkata, Scannable dynamic circuit latch.
  49. Qureshi, Imran, Scannable fast dynamic register.
  50. Masleid, Robert P.; Burr, James B., Stacked inverter delay chain.
  51. Chang, Leland; Montoye, Robert K.; Nakamura, Yutaka, Time division multiplexed limited switch dynamic logic.
  52. Chang, Leland; Montoye, Robert K.; Nakamura, Yutaka, Time division multiplexed limited switch dynamic logic.
  53. Pitkethly, Scott; Masleid, Robert P., Triple latch flip flop system and method.
  54. Pitkethly,Scott; Masleid,Robert P., Triple latch flip flop system and method.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로