초록 ▼

A digital write-and-read method and a signal processing apparatus wherein a write encoder includes a bit distribution circuit for dividing an input data block into n (n: 2 or more) series of bit strings and outputting them in parallel, a first coding circuit for executing predetermined coding for ea

A digital write-and-read method and a signal processing apparatus wherein a write encoder includes a bit distribution circuit for dividing an input data block into n (n: 2 or more) series of bit strings and outputting them in parallel, a first coding circuit for executing predetermined coding for each of data series so distributed and a second coding circuit for converting the output bit series D1 to D3 of the first coding circuit to an n-bit channel code by looking up the previous channel code information, and wherein the second coding circuit executes coding by using a combination having a large Euclidean distance in a partial response equalization output taking inter-symbol interference of at least three bits into consideration as a pair.

대표청구항 ▼

[ What is claimed is:] [1.] A digital recording method comprising:a first coding step of distributing serially digital data to be recorded in such a manner as to constitute n (where n is 2 or more) data series each having an inherent bit length, arranging each of said data series to the same bit len

[ What is claimed is:] [1.] A digital recording method comprising:a first coding step of distributing serially digital data to be recorded in such a manner as to constitute n (where n is 2 or more) data series each having an inherent bit length, arranging each of said data series to the same bit length by adding an coding bit or bits to at least one of said data series having a short bit length, and serially generating n-bit parallel data by outputting one bit each from said n data series; anda second coding step of converting n-bit input data obtained from said first coding step to n-bit channel codes determined by the bit pattern of said input data and by the state of channel codes of a plurality of bits that have been already converted;wherein the conversion rule of said second coding step associates the channel codes in such a manner that a partial response equalization output of each of said channel codes, which takes inter-symbol interference of a least 3 bits into consideration, has an Euclidean distance of at least 16 for each combination of two bit patterns having a predetermined Hamming distance at bit positions corresponding to said data series not having the coding bit or at bit positions corresponding to said data series having the shortest coding bit length, for those bit patterns which said n-bit input data can take.