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Inter-bus bridge circuit with integrated memory port

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-013/00
출원번호 US-0674592 (1996-06-28)
발명자 / 주소
  • Corrigan Brian E.
  • Rymph Alan D.
출원인 / 주소
  • LSI Logic Corporation
대리인 / 주소
    Fishman
인용정보 피인용 횟수 : 24  인용 특허 : 30

초록

A bus bridge circuit having a memory port integrated therewith for upstream memory access independent of the activity on the primary bus connected to the bridge circuit. In a preferred embodiment, the present invention adds a memory port to a PCI bridge circuit usable for upstream data transfers to

대표청구항

[ What is claimed is:] [1.] A PCI to PCI bus bridge comprising:a primary PCI bus port connecting said bus bridge to a primary PCI bus, wherein said primary PCI bus communicates with a processor coupled to a processor bus;a secondary PCI bus port connecting said bus bridge to a secondary PCI bus and

이 특허에 인용된 특허 (30)

  1. Kinoshita Tsuneo (Kokubunji JPX), 32-bit personal computer using a bus width converter and a latch for interfacing with 8-bit and 16-bit microprocessors.
  2. Cohen Ariel (Zichron-Yaacov ILX) Holland William G. (Cary NC) Logan Joseph F. (Raleigh NC) Parash Avi (Ramat-Yishay ILX), Add-in board with enable-disable expansion ROM for PCI bus computers.
  3. Amini Nader (Boca Raton FL) Bland Patrick M. (Delray Beach FL) Boury Bechara F. (Boca Raton FL) Hofmann Richard G. (Boynton Beach FL) Lohman Terence J. (Boca Raton FL), Arbitration logic for multiple bus computer system.
  4. Benedict Melvin Kent (Cary NC) Buckland Patrick Allen (Austin TX) Kelley Richard Allen (Apex NC) Neal Danny Marvin (Round Rock TX) Oman Price Ward (Raleigh NC) Waters Carl Raymond (Cary NC), Autodocking hardware for installing and/or removing adapter cards without opening the computer system cover.
  5. Smith Michael G. (Tustin CA), Automatic control of distributed DMAs in a PCI bus system supporting dual ISA buses.
  6. Bland Patrick M. (Austin TX) Hofmann Richard G. (Cary NC) Katz Sagi (Haifa ILX) Moeller Dennis (Boca Raton FL) Venarchick Lance M. (Boca Raton FL), Bridge between two buses of a computer system that determines the location of memory or accesses from bus masters on one.
  7. Tsuchiya Haruhiko (Sagamihara JPX), Bus arbitration system for concurrent use of a system bus by more than one device.
  8. Kirk John (Boxboro MA) Narhi Larry (Bolton MA), Bus data path control scheme.
  9. Amini Nader (Boca Raton FL) Kohli Ashu (Delray Beach FL) Santos Gregory N. (Boca Raton FL), Bus-to-bus bridge for a multiple bus information handling system that optimizes data transfers between a system bus and.
  10. Amini Nader (Boca Raton FL) Kohli Ashu (Delray Beach FL) Santos Gregory N. (Boca Raton FL), Bus-to-bus read prefetch logic for improving information transfers in a multi-bus information handling system (bus-to-bu.
  11. Jennings William E. (Cary NC) Chan Roland G. (Mountain View CA) Wong John L. (Belmont CA), Computer system with cascaded peripheral component interconnect (PCI) buses.
  12. Solomon Gary (Hillsboro OR), Configuration data loopback in a bus bridge circuit.
  13. Searls Ronald C. (Dade City FL), Data buss interface and expansion system.
  14. Kobayashi Souichi (Itami JPX) Saito Yuichi (Itami JPX), Data processor with bus-sizing function.
  15. Stewart John W. (Wichita KS) Gates Dennis E. (Wichita KS) DeKoning Rodney A. (Wichita KS) Rink Curtis W. (Wichita KS), Disk array storage system architecture for parity operations simultaneous with other data operations.
  16. DuLac Keith B. (Derby KS) Weber Bret S. (Wichita KS), Disk controller having host interface and bus switches for selecting buffer and drive busses respectively based on confi.
  17. Mote ; Jr. L. Randall (Laguna Hills CA), High impedance test mode for JTAG.
  18. Young Bruce (Tigard OR) Coulson Rick (Portland OR), Intelligent bus bridge for input/output subsystems in a computer system.
  19. Wolford Jeff W. (Spring TX) Fry Walter G. (Spring TX), Method and apparatus for concurrency of bus operations.
  20. Kennedy Barry (Santa Ana CA), Method and apparatus for expanding a backplane interconnecting bus in a multiprocessor computer system without additiona.
  21. Narain Bikas (Gilbert AZ), Method and apparatus for improving instruction tracing operations in a computer system.
  22. Rabe Jeffrey L. (Gold River CA) Sadhasivan Sathyamurthi (El Dorado Hills CA), Method and apparatus for sequencing buffers for fast transfer of data between buses.
  23. Heil Thomas F. (Easley SC) Walrath Craig A. (Easley SC) Hawkey Jeff A. (Easley SC) Pike Jim D. (Greenville SC), Multi-port processor with peripheral component interconnect port and rambus port.
  24. Testa James (Mountain View CA) Bechtolsheim Andreas (Stanford CA), Multiple bus architecture for flexible communication among processor modules and memory subsystems and specialized subsy.
  25. Jibbe Mahmoud K. (Wichita KS) McCombs Craig C. (Wichita KS) Thompson Kenneth J. (Wichita KS), Multiple configuration data path architecture for a disk array controller.
  26. Chen Karl C. (San Jose CA) Cheng Yu-Ping (San Jose CA), Multiple peripheral adapter device driver architecture.
  27. Stancil Charles J. (Tomball TX) Vaughn William M. (Houston TX) Wolford Jeff W. (Spring TX), Non-conforming PCI bus master timing compensation circuit.
  28. Bell D. Michael (Beaverton OR), PCI split transactions utilizing dual address cycle.
  29. Dunstan Robert A. (Beaverton OR) Shimoda Marion H. (Aloha OR) Silvester Kelan C. (Portland OR) Sun Jiming (Spring TX), Power management coordinator system and interface.
  30. Tipley Roger E. (Houston TX), Split transaction protocol for the peripheral component interconnect bus.

이 특허를 인용한 특허 (24)

  1. Davies,Ian Robert; Maine,Gene; Pecone,Victor Key, Apparatus and method for adopting an orphan I/O port in a redundant storage controller.
  2. Maine,Gene, Broadcast bridge apparatus for transferring data to redundant memory subsystems in a storage controller.
  3. Ansari, Ahmad R., Bus protocol for efficiently transferring vector data.
  4. Ashmore, Paul Andrew; Davies, Ian Robert; Maine, Gene; Vedder, Rex Weldon, Certified memory-to-memory data transfer between active-active raid controllers.
  5. Bronson, Timothy C.; Gilda, Glenn D.; Sheplock, John M.; Williams, Phillip G., Data caching on bridge following disconnect.
  6. Hobson, Richard F.; Ressl, Bill; Dyck, Allan R., Hierarchical bus structure and memory access protocol for multiprocessor systems.
  7. Hobson,Richard F.; Ressl,Bill; Dyck,Allan R., Hierarchical bus structure and memory access protocol for multiprocessor systems.
  8. Dastidar,Jaideep; Hensley,Ryan J.; Ruhovets,Michael; Lam,An H., Inter-queue ordering mechanism.
  9. Davies, Ian Robert; Pecone, Victor Key, Method for adopting an orphan I/O port in a redundant storage controller.
  10. Davies,Ian Robert; Maine,Gene; Vedder,Rex Weldon, Method for efficient inter-processor communication in an active-active RAID system using PCI-express links.
  11. Klein Dean A., Method for providing and operating upgradeable cache circuitry.
  12. Pecone Victor Key ; Swanson Dwayne Howard, Modular bus bridge system compatible with multiple bus pin configurations.
  13. Zhou, Zhinan; Wong, Kimchung Arthur, Multi-port PCI-to-PCI bridge with combined address FIFOs but separate data FIFOs for concurrent transactions.
  14. Boily,Patrick, PCI bridge and data transfer methods.
  15. Nayak, Anup; Lulla, Navaz; Ighani, Ramin; Nema, Rajiv, PLD configuration architecture.
  16. Hobson, Richard F.; Ressl, Bill; Dyck, Allan R., Processor cluster architecture and associated parallel processing methods.
  17. Hobson, Richard F.; Ressl, Bill; Dyck, Allan R., Processor cluster architecture and associated parallel processing methods.
  18. Ashmore,Paul Andrew; Davies,Ian Robert; Maine,Gene, RAID system for performing efficient mirrored posted-write operations.
  19. Ashmore, Paul Andrew, Redundant storage controller system with enhanced failure analysis capability.
  20. Davies, Ian Robert, Safe message transfers on PCI-Express link from RAID controller to receiver-programmable window of partner RAID controller CPU memory.
  21. Lange Ronald Edwin, Selective data read-ahead in bus-to-bus bridge architecture.
  22. Larson,Thane M.; Yates,Kirk, System and method for presence detect and reset of a device coupled to an inter-integrated circuit router.
  23. Davies, Ian Robert, System and method for sharing SATA drives in active-active RAID controller system.
  24. Dean A. Klein, Upgradeable cache circuit using high speed multiplexer.
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