초록 ▼

A process applicable to the production of monocrystalline films improves on the Smart-Cut.RTM. process by using an etch stop layer in conjunction with the Smart-Cut.RTM. process. Because of the etch stop layer, no chemical-mechanical polishing (CMP) is required after fabrication. Thus, the thickness

A process applicable to the production of monocrystalline films improves on the Smart-Cut.RTM. process by using an etch stop layer in conjunction with the Smart-Cut.RTM. process. Because of the etch stop layer, no chemical-mechanical polishing (CMP) is required after fabrication. Thus, the thickness and smoothness of the device layer in the fabricated silicon on insulator (SOI) substrate is determined by the uniformity and smoothness of the deposited layers and wet etch selectivity, as opposed to the CMP parameters. Therefore, the smoothness and uniformity of the device layer are improved.

대표청구항 ▼

[ What is claimed:] [25.] A method for forming a thin silicon on insulator structure, comprising:providing a first wafer comprising a silicon substrate;forming an etch stop layer having a thickness upon said first wafer;forming a device layer having a thickness on said etch stop layer;forming a bond

[ What is claimed:] [25.] A method for forming a thin silicon on insulator structure, comprising:providing a first wafer comprising a silicon substrate;forming an etch stop layer having a thickness upon said first wafer;forming a device layer having a thickness on said etch stop layer;forming a bonding layer on said device layer;implanting hydrogen ions into said silicon substrate to form a buried hydrogen-rich layer therein;forming a layer of silicon dioxide on an exposed surface of a second wafer;wetting said bonding layer and said silicon dioxide layer;bringing said bonding layer and said silicon dioxide layer into contact;compressing said bonding layer and said silicon dioxide layer to form a hydrophilic bond therebetween;annealing said bonded first and second wafers at a first temperature;separating said bonded wafers along said buried hydrogen-rich layer so that said second wafer has a top surface layer comprising Si from said first wafer;annealing said second wafer having said top surface layer to a second temperature;etching said top surface layer in a first etchant which does not appreciably attack a remaining part of said etch stop layer; andetching said etch stop layer in a second etchant which does not appreciably attack a remaining part of said device layer;whereby underlying portions of said device layer remain on the second wafer to form the thin silicon on insulator structure.