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Method of stress testing integrated circuit having memory and integrated circuit having stress tester for memory thereof

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G11C-007/00
출원번호 US-0862969 (1997-05-23)
발명자 / 주소
  • So Jason Siucheong
출원인 / 주소
  • STMicroelectronics, Inc.
대리인 / 주소
    Galanthay
인용정보 피인용 횟수 : 5  인용 특허 : 66

초록

An integrated circuit having enhanced testing capabilities and a method of testing an integrated circuit are provided. The integrated circuit preferably includes a substrate and a memory block on the substrate. The memory block preferably has a plurality of memory cells arranged in a plurality of ro

대표청구항

[ That which is claimed:] [1.] An integrated circuit having enhanced testing capabilities, said integrated circuit comprising:a substrate;a memory block on said substrate comprising a plurality of memory cells arranged in a plurality of rows and a plurality of columns within a defined area on said s

이 특허에 인용된 특허 (66)

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이 특허를 인용한 특허 (5)

  1. Lawrence Allen B., Method and system for identifying a memory module configuration.
  2. Shubat,Alex, System and method for providing adjustable read margins in a semiconductor memory.
  3. Shubat,Alex, System and method for providing adjustable read margins in a semiconductor memory.
  4. Kawasaki,Tatsuya, Test circuit for memory.
  5. Teoh,Wan Yen; Law,Che Seong, Testing for operating life of a memory device with address cycling using a gray code sequence.
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