초록 ▼

An integrated cached disk array includes host to global memory (front end) and global memory to disk array (back end) interfaces implemented with dual control processors configured to share substantial resources. The dual processors each access independent control store RAM, but run the same process

An integrated cached disk array includes host to global memory (front end) and global memory to disk array (back end) interfaces implemented with dual control processors configured to share substantial resources. The dual processors each access independent control store RAM, but run the same processor independent control program using an implementation that makes the hardware appear identical from both the X and Y processor sides.

대표청구항 ▼

[ What is claimed is:] [1.] A method of sharing a shared resource between a first control processor and a second control processor, said shared resource including a first processor resource portion and a second processor resource portion, said method comprising the steps of:configuring said first co

[ What is claimed is:] [1.] A method of sharing a shared resource between a first control processor and a second control processor, said shared resource including a first processor resource portion and a second processor resource portion, said method comprising the steps of:configuring said first control processor and said second control processor to run a common control program accessible to each of said first control processor and said second control processor, said common control program acquiring access to said shared resource via a first address in said common control program;translating said first address to one of a first processor resource portion address and a second processor resource portion address based on a field of said first address, and translating said first address to said first processor resource portion address if said field of said first address is in a first state and translating said first address to said second processor resource portion address if said field of said first address is in a second state,wherein both of said first control processor and said second control processor run said common control program and accessing of one of said first processor resource portion and said second processor resource portion is effected in a manner transparent to said first control processor and said second control processor.