$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Interconnect structure with hard mask and low dielectric constant materials 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/485
출원번호 US-0670624 (1996-06-26)
발명자 / 주소
  • Chiang Chien
  • Pan Chuanbin
  • Ochoa Vicky M.
  • Fang Sychyi
  • Fraser David B.
  • Sum Joyce C.
  • Ray Gary William
  • Theil Jeremy A.
출원인 / 주소
  • Intel Corporation
대리인 / 주소
    Blakely, Sokoloff, Taylor & Zafman LLP
인용정보 피인용 횟수 : 64  인용 특허 : 13

초록

An interconnect system is provided. The interconnect system includes a silicon substrate and a first dielectric layer formed upon the silicon substrate. The interconnect system also includes a first level of at least two electrically conductive lines formed upon the first dielectric layer. The inter

대표청구항

[ What is claimed is:] [1.] An interconnect system comprising:a silicon substrate;a first dielectric layer formed upon said silicon substrate;a first level of at least two electrically conductive lines formed upon said first dielectric layer;a first region with a low dielectric constant material for

이 특허에 인용된 특허 (13)

  1. Ireland Philip J. (Nampa ID), Double mask process for forming trenches and contacts during the formation of a semiconductor memory device.
  2. O\Connor Loretta J. (Westford VT) Previti-Kelly Rosemary A. (Richmond VT) Reen Thomas J. (Essex Junction VT), Metallized vias in polyimide.
  3. Nowak Edward D. (Pleasanton CA), Method for self-aligned punchthrough implant using an etch-back gate.
  4. Nulty James E. (San Jose CA) Trammel Pamela S. (San Jose CA), Method of etching an oxide layer.
  5. Chang Chorng-Ping (Union County NJ) Lee Kuo-Hua (Wescosville PA) Liu Chun-Ting (Wescosville PA) Liu Ruichen (Warren NJ), Method of fabricating gate stack having a reduced height.
  6. Figura Thomas A. (Boise ID) Prall Kirk D. (Boise ID), Method of forming contact areas between vertical conductors.
  7. Jeng Shin-Puu (Plano TX), Planarized multi-level interconnect scheme with embedded low-dielectric constant insulators.
  8. Burke Peter A. (Milton VT) Leach Michael A. (Milpitas CA), Polishstop planarization structure.
  9. Havemann Robert H. (Garland TX) Gnade Bruce E. (Dallas TX) Cho Chih-Chen (Richardson TX), Porous dielectric material with a passivation layer for electronics applications.
  10. Jeng Shin-Puu (Plano TX), Porous insulator for line-to-line capacitance reduction.
  11. Nishimura Hiroyuki (Hyogo JPX) Adachi Hiroshi (Hyogo JPX) Adachi Etsushi (Hyogo JPX) Yamamoto Shigeyuki (Hyogo JPX) Minami Shintaro (Hyogo JPX) Harada Shigeru (Hyogo JPX) Tajima Toru (Hyogo JPX) Hagi, Semiconductor device having a multilayer interconnection structure.
  12. Mizushima Kazuyuki (Tokyo JPX), Semiconductor integrated circuit having a multilayer wiring structure.
  13. Kim Manjin J. (Schenectady NY) Griffing Bruce F. (Schenectady NY) Skelly David W. (Burnt Hills NY), Unframed via interconnection with dielectric etch stop.

이 특허를 인용한 특허 (64)

  1. Chung Henry, Advanced fabrication method of integrated circuits with borderless vias and low dielectric-constant inter-metal dielectrics.
  2. Maex, Karen; Donaton, Ricardo A.; Baklanov, Michael; Vanhaelemeersch, Serge; Struyf, Herbert; Schaekers, Marc, Anisotropic etching of organic-containing insulating layers.
  3. Vanhaelemeersch, Serge; Baklanov, Mikhail Rodionovich, Anisotropic etching of organic-containing insulating layers.
  4. Vanhaelemeersch, Serge; Baklanov, Mikhail Rodionovich, Anisotropic etching of organic-containing insulating layers.
  5. Chien Wen-Chen,TWX ; Lo Chi-Hsin,TWX ; Yu Ding-Jeng,TWX, Approach for aluminum bump process.
  6. Choi,Chee Hong, Copper line of semiconductor device and method for forming the same.
  7. Naik Mehul B. ; Weidman Tim ; Sugiarto Dian ; Zhao Allen, Damascene structure fabricated using a layer of silicon-based photoresist material.
  8. Naik, Mehul B.; Weidman, Tim; Sugiarto, Dian; Zhao, Allen, Damascene structure fabricated using a layer of silicon-based photoresist material.
  9. Huang Yimin,TWX ; Yew Tri-Rung,TWX, Dual damascene process.
  10. Dobuzinsky, David Mark; Khan, Babar Ali; Liu, Joyce C.; Wensley, Paul R.; Yu, Chienfan, Dual layer hard mask for eDRAM gate etch process.
  11. Farrar,Paul A., Integrated circuit cooling system and method.
  12. Havemann Robert H. ; Jain Manoj K., Integrated circuit insulator and structure using low dielectric insulator material including HSQ and fluorinated oxide.
  13. Somnath S. Nag ; Changming Jin ; Wei-Yung Hsu ; Guoqiang Xing, Integration of fluorinated dielectrics in multi-level metallizations.
  14. Chiang Chien ; Fraser David B., Interconnect structure using a combination of hard dielectric and polymer as interlayer dielectrics.
  15. Zhao, Bin; Brongo, Maureen R., Interconnect with low dielectric constant insulators for semiconductor integrated circuit manufacturing.
  16. Cox William P., Low dielectric constant material and method of application to isolate conductive lines.
  17. Rangarajan, Bharath; Subramanian, Ramkumar; Templeton, Michael K., Low k ILD process by removable ILD.
  18. Yu, Jick; Choi, Chi Hing, Metal to ILD adhesion improvement by reactive sputtering.
  19. Weber, Detlef, Metallization arrangement for semiconductor structure and corresponding fabrication method.
  20. Oiao Jianmin ; Nulty James, Method and structure for making self-aligned contacts.
  21. Fornof, Ann Rhea-Helene; Gates, Stephen McConnell; Hedrick, Jeffrey Curtis; Nitta, Satyanarayana V.; Purushothaman, Sampath; Tyberg, Christy Sensenich, Method for dual-damascence patterning of low-k interconnects using spin-on distributed hardmask.
  22. Meng-Chang Liu TW; Yuan-Lung Liu TW, Method for forming a top interconnection level and bonding pads on an integrated circuit chip.
  23. Ebrahim Andideh ; Qing Ma ; Quan Tran ; Steve Towle, Method for making a semiconductor device having a low-k dielectric layer.
  24. Chris Ting TW; Janet Yu TW, Method for metal etch using a dielectric hard mask.
  25. Chiu, Hsien-Kuang; Chen, Fang-Chang; Tao, Hun-Jan; Chiu, Yuan-Hung; Chen, Jeng-Horng, Method of etching a silicon containing layer using multilayer masks.
  26. Cronin John E. ; Luther Barbara J., Method of fabricating a stacked via in copper/polyimide beol.
  27. Weidman, Timothy; Bekiaris, Nikolaos; Chang, Josephine; Nguyen, Phong H., Method of forming a dual damascene structure using an amorphous silicon hard mask.
  28. Bekiaris,Nikolaos; Weidman,Timothy; Armacost,Michael D.; Naik,Mehul B., Method of forming a dual damascene structure utilizing a three layer hard mask structure.
  29. Suzuki, Mieko; Kubo, Akira, Method of forming polish stop by plasma treatment for interconnection.
  30. Petrarca Kevin Shawn ; Knickerbocker Sarah ; Liu Joyce C. ; Mih Rebecca D., Method of producing heat dissipating structure for semiconductor devices.
  31. Serguei Ianovitch SG, Method of residual resist removal after etching of aluminum alloy filmsin chlorine containing plasma.
  32. Phi L. Nguyen ; Lawrence D. Wong, Method of via patterning utilizing hard mask and stripping patterning material at low temperature.
  33. Huang Kuo Ching,TWX ; Chiang Wen-Chuan,TWX ; Wu Cheng-Ming,TWX ; Lee Yu-Hua,TWX, Method to form a recess free deep contact.
  34. Victor Seng Keong Lim SG; Feng Chen SG; Wang Ling Goh SG, Method to prevent CU dishing during damascene formation.
  35. Chen Feng,SGX ; Teo Rick,SGX ; Chan Lap, Method to reduce dishing in metal chemical-mechanical polishing.
  36. Abadeer, Wagdi W.; Chatty, Kiran V.; Gauthier, Jr., Robert J.; Rankin, Jed H.; Robison, Robert; Shi, Yun; Tonti, William R., Methods for forming back-end-of-line resistive semiconductor structures.
  37. Park,Tae Hee, Methods of forming metal lines in semiconductor devices.
  38. Mototsugu Okushima JP, Multilayer wiring structure and semiconductor device having the same, and manufacturing method therefor.
  39. Okushima Mototsugu,JPX, Multilayer wiring structure and semiconductor device having the same, and manufacturing method therefor.
  40. Foote David K. ; Ngo Minh Van ; Lyons Christopher F. ; Wang Fei ; Lee Raymond T. ; En William G. ; Chen Susan H. ; Chan Darin A., Multipurpose cap layer dielectric.
  41. Farrar,Paul A., Packaging of electronic chips with air-bridge structures.
  42. Kun-Ming Huang TW; Cheng-Wei Lee TW; Ding-Jeng Yu TW, Process improvement for the creation of aluminum contact bumps.
  43. Wang, Shi-Qing; Dunne, Jude; Figge, Lisa, Process of using siloxane dielectric films in the integration of organic dielectric films in electronic devices.
  44. Wang, Shi-Qing; Dunne, Jude; Figge, Lisa, Process of using siloxane dielectric films in the integration of organic dielectric films in electronic devices.
  45. Dalton, Timothy J.; Jahnes, Christopher V.; Liu, Joyce C.; Purushothaman, Sampath, Protective hardmask for producing interconnect structures.
  46. Tsai Ming-Hsing,TWX ; Shue Shau-Lin,TWX, Self aligned dual damascene process and structure with low parasitic capacitance.
  47. Usami,Tatsuya; Morita,Noboru; Ohto,Koichi, Semiconductor device and method for manufacturing same.
  48. Andideh, Ebrahim; Ma, Qing; Tran, Quan; Towle, Steve, Semiconductor device having a low-K dielectric layer.
  49. Hideyo Haruhana JP; Hiroyuki Amishiro JP; Akihiko Harada JP, Semiconductor device having an improved multi-layer interconnection structure and manufacturing method thereof.
  50. Dunham, Timothy G.; Landis, Howard S.; Motsiff, William T., Stacked fill structures for support of dielectric layers.
  51. Dunham, Timothy G.; Landis, Howard S.; Motsiff, William T., Stacked fill structures for support of dielectric layers.
  52. Cronin, John E.; Luther, Barbara J., Stacked via in copper/polyimide BEOL.
  53. Dodabalapur Ananth, Thin film transistors.
  54. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  55. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  56. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  57. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  58. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  59. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  60. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  61. Chen-Hua Yu TW; Syun-Ming Jang TW; Tsu Shih TW; Anthony Yen TW; Jih-Chuyng Twu TW, Use of PE-SiON or PE-Oxide for contact or via photo and for defect reduction with oxide and w chemical-mechanical polish.
  62. Eissa, Mona M.; Yocum, Troy A., Wet clean of organic silicate glass films.
  63. Miyamoto, Takaaki, Wiring structure in semiconductor device and method for forming the same.
  64. Takaaki Miyamoto JP, Wiring structure in semiconductor device and method for forming the same.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로