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Lateral etch inhibited multiple for forming a via through a microelectronics layer susceptible to etching within a fluor 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • B08B-006/00
  • H01L-021/302
출원번호 US-0998635 (1997-12-29)
발명자 / 주소
  • Yu Chen-Hua,TWX
출원인 / 주소
  • Taiwan Semiconductor Manufacturing Company, Ltd., TWX
대리인 / 주소
    Saile
인용정보 피인용 횟수 : 96  인용 특허 : 5

초록

A method for forming within a microelectronics fabrication a via through a microelectronics layer formed of a material susceptible to sequential etching employing a fluorine containing plasma etch method followed by an oxygen containing plasma etch method. There is first provided a substrate employe

대표청구항

[ What is claimed is:] [1.] A method for forming within a microelectronics fabrication a via through a microelectronics layer formed of a material susceptible to sequential etching employing a fluorine containing plasma etch method followed by an oxygen containing plasma etch method comprising:provi

이 특허에 인용된 특허 (5)

  1. Dalal Hormazdyzr D. (Wappingers Falls NY) Patnaik Bisweswar (Wappingers Falls NY) Sarkary Homi G. (Hopewell Junction NY), Forming interconnections for multilevel interconnection metallurgy systems.
  2. Chen Song (Sunnyvale CA) Chen Chun Ya (Saratoga CA), Method for via formation with reduced contact resistance.
  3. Wootton Phil (Hamilton GB6) Morland Graeme (Falkirk TX GB6) Mautz Karl E. (Austin TX) Dalziel John (Wishaw GB6), Method of removing photo resist.
  4. Chang Hsien-Wen (Hsin-Chu TWX), Solving the poison via problem by adding N2 plasma treatment after via etching.
  5. Jones Stephen A. (Austin TX) Garg Shyam G. (Austin TX), Thermal oxide etch technique.

이 특허를 인용한 특허 (96)

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