초록 ▼

Top die pads are electrically relocated by forming holes through a semiconductor wafer between device active regions. An electrically insulating layer is formed over all exposed surfaces of the wafer, including within the holes, and openings are made in the insulating layer for access to the top int

Top die pads are electrically relocated by forming holes through a semiconductor wafer between device active regions. An electrically insulating layer is formed over all exposed surfaces of the wafer, including within the holes, and openings are made in the insulating layer for access to the top interconnection pads. The wafer and holes are metallized and patterned to form bottom interconnection pads electrically connected to corresponding top interconnection pads by metallization extending within the holes. A dicing saw having a kerf width less than the diameter of the holes is employed to separate the individual devices. For accurate position alignment of repatterned die, an alignment structure, such as projecting pins or an egg crate structure, engages the die, and alignment pads can be patterned on the die.

대표청구항 ▼

[ What is claimed is:] [1.] A method for making an array of closely-spaced devices, said method comprising:providing a semiconductor wafer having front and rear major surfaces, the wafer including a plurality of active device regions separated by scribe lanes, with top interconnection pads on the fr

[ What is claimed is:] [1.] A method for making an array of closely-spaced devices, said method comprising:providing a semiconductor wafer having front and rear major surfaces, the wafer including a plurality of active device regions separated by scribe lanes, with top interconnection pads on the front major surface;forming holes through the wafer within the scribe lanes;forming an electrically insulating layer on all exposed surfaces of the wafer, including within the holes, with openings in the insulating layer for access to the top interconnection pads;metallizing and patterning the wafer and the holes to form bottom interconnection pads and alignment pads on the rear major surface, the bottom interconnection pads electrically connected to corresponding interconnection pads by metallization extending within the holes;employing a dicing saw having a kerf width less than the diameter of the holes to saw within at least some of the scribe lanes to separate the wafer into segments each including at least one device active region;providing a substrate having at least two electrical connection pads positioned for mating with the alignment pads;forming a rigid alignment structure on the substrate and projecting from the substrate for mechanical engagement with the devices; andplacing the devices on the substrate and attaching the alignment pads to the electrical connection pads, whereby the rigid alignment structure provides accurate position alignment.