초록 ▼

One embodiment of the present invention provides a memory system that allows more than one cycle of memory latency for accesses to a synchronously accessed memory. In this embodiment, the memory system includes a memory with a clocked interface and a corresponding clock input. It also includes an ou

One embodiment of the present invention provides a memory system that allows more than one cycle of memory latency for accesses to a synchronously accessed memory. In this embodiment, the memory system includes a memory with a clocked interface and a corresponding clock input. It also includes an output register for storing data outputted from the memory during a read operation. The output register and the memory are coupled together by a data path, for transferring data between the memory and the output register. In this embodiment, the memory system further includes a clock signal coupled to the clocked interface of the memory. The clock signal feeds through a delay element into a clock input of the output register. This causes the output register to receive a delayed clock signal, thereby providing more than one clock cycle of time for data to be read from the memory and latched in the output register. In another embodiment, the present invention provides an input register, for inputting data during write operations. This input register similarly receives a delayed clock signal, which functions as an advanced clock signal from the preceding clock cycle to provide more than one clock cycle of latency for write accesses to memory.

대표청구항 ▼

[ What is claimed is:] [1.] A memory controller, that provides more than one clock cycle of memory latency for accesses to a memory with a synchronous interface, comprising:a processor interface, for coupling to a processor;an input register including a clock input, for storing data to be inputted i

[ What is claimed is:] [1.] A memory controller, that provides more than one clock cycle of memory latency for accesses to a memory with a synchronous interface, comprising:a processor interface, for coupling to a processor;an input register including a clock input, for storing data to be inputted into the memory during a write operation;an output register including a clock input, for storing data outputted from the memory during a read operation;a data path coupled between the processor interface and the input and output registers, for transferring data between the processor interface and the input and output registers; anda controller coupled to the processor interface, the input register and the output register, for controlling the transfer of data between a processor coupled to the processor interface and a memory coupled to the input and output registers, the controller including a first delay element, with an input coupled to a clock signal, and an output coupled to the clock input of the output register, so that the output register receives a delayed clock signal.