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Adaptive power failure recovery 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-011/00
출원번호 US-0794235 (1997-01-30)
발명자 / 주소
  • Smith Gerald E.
출원인 / 주소
  • AIWA Co., Ltd., JPX
대리인 / 주소
    Graham & James LLP
인용정보 피인용 횟수 : 38  인용 특허 : 19

초록

A RAID system that uses non-volatile random access memory (NVRAM) to greatly reduce the chance of loss of data due to an AC power failure. This RAID system has two write modes. In a normal write mode, a host computer receives a write confirmation once an array controller receives data from the host

대표청구항

[ What is claimed is:] [1.] A data storage system comprising:a non-volatile memory having a plurality of segments; andan array controller for coupling to a UPS and periodically polling a power outage flag in the UPS, for coupling to a host CPU, for coupling to a power source, and for coupling to a p

이 특허에 인용된 특허 (19)

  1. Pusic Vladi (San Jose CA) George Benjamin T. (Sunnyvale CA) Smith Monte E. (St. Paul MN) Johnson Craig B. (Shoreview MN), Cache/disk file status indicator with data protection feature.
  2. Horning Randall (Longmont CO), Data protection system using different levels of reserve power to maintain data in volatile memories for any period of t.
  3. Lasker Jeffrey M. (Marlboro MA) McGillis James M. (Franklin MA), Disk controller with volatile and non-volatile cache memories.
  4. Noya Eric S. (Groton MA) Arnott Randy M. (Clinton MA), Method and apparatus for a backup power controller for volatile random access memory.
  5. Binford Charles D. (Wichita KS) Gaertner Mark A. (Woodbury MN) Denny Steven P. (El Dorado KS), Method for maintaining parity-data consistency in a disk array.
  6. Guillot Pierre (Geneva CHX), Non-volatile memory system.
  7. Ergott ; Jr. Harold L. (Fountain Hills AZ) Bruder John F. (Phoenix AZ) Peters Robert E. (Tempe AZ) Rainwater Sam L. (Tempe AZ), Non-volatile semiconductor memory with SCRAM hold cycle prior to SCRAM-to-E2PROM backup transfer.
  8. Berenguel Leo P. (Fremont CA) Reykjalin John (Berkeley CA), Nonvolatile ramdisk memory.
  9. Stallmo David C. (Boulder CO), On-line reconstruction of a failed redundant array system.
  10. Stallmo David C. (Boulder CO) Brant William A. (Boulder CO) Gordon David (Boulder CO), On-line restoration of redundancy information in a redundant array system.
  11. Holtz Earl B. (Huntington CT) Lay Roger F. (Newtown CT) Manduley Flavio M. (Woodbury CT) Moody Howard J. (Monroe CT 4), Power failure memory support system.
  12. White Dave (San Jose CA) Lee Yen W. (San Jose CA) Ang Rod (San Jose CA) Barbieri Ray (Campbell CA) Chen James (Taipei CA TWX) Lee Suh C. (Palo Alto CA), Power-management system for a computer.
  13. Fujita Kenji (Odawara JPX) Nakao Toshiyuki (Hadano JPX) Yamagata Hirotsugu (Odawara JPX) Saze Nobuyuki (Odawara JPX), Semiconductor memory.
  14. Davis John E. (Reseda CA), Shadow memory system for storing variable backup blocks in consecutive time periods.
  15. Finger Eugene P. (Brewster NY), Solid-state cumulative operations measurement system.
  16. Islam S. M. Rezaul (Boca Raton FL), System and method for command queuing on raid levels 4 and 5 parity drives.
  17. Lui Albert (San Jose CA) Walker Mark S. (Los Gatos CA), System and method for ensuring write data integrity in a redundant array data storage system.
  18. Langer Dale R. (Raleigh NC) Messer G. John (Raleigh NC), Uninterrupted power supply (UPS) system interfacing with communications network.
  19. Byrd Kerry (Falls Church VA), Work-saving system for preventing loss in a computer due to power interruption.

이 특허를 인용한 특허 (38)

  1. James, Owen Michael; Giorgis, Daniel; Sublett, John, Approach for data integrity in an embedded device environment.
  2. Dunstan, Robert A.; Selseth, Larry D.; Nowlin, Dan H., BIOS for saving and restoring operational state in the absence of AC power.
  3. Matsuda, Shinnosuke; Ohyama, Sadayuki; Yuasa, Kentaro; Ishii, Takanori; Kawano, Yoko; Hanaoka, Yuji; Tsukamoto, Nina; Muro, Tomoharu, Backup method and disk array apparatus.
  4. Floro, William Edward; Priore, Frank Joseph, Battery backed memory with battery disconnect for improved battery life.
  5. Floro, William Edward; Schultz, Ronald Edwin, Battery backed memory with low battery voltage trip, disconnect and lockout.
  6. Mustafa Mazin A. ; Chaiken Craig L., Computer system with power loss protection mechanism.
  7. Abraham, Moby J.; Anupindi, Lakshmana M.; Skinner, R. Brian B.; Rizzo, James A.; Jander, Mark J., Control logic design to support USB cache offload.
  8. Dawkins, George John; Kulkarni, Ashwini; Lee, Van Hoa; McIntosh, Gordon D.; Patel, Kanisha, Critical datapath error handling in a multiprocessor architecture.
  9. Takahashi,Fumikazu; Nemoto, legal representative,Isao; Kanouda,Akihiko; Hamaogi,Masahiro; Takahashi,Yoshihide; Nemoto,Minehiro, DC backup power supply system and disk array using same.
  10. Takahashi, Fumikazu; Nemoto, Minehiro; Nemoto, legal representative, Isao; Kanouda, Akihiko; Hamaogi, Masahiro; Takahashi, Yoshihide, DC backup power supply system, a disk array and a DC backup power supply.
  11. Breckner, Robert E.; Schlottmann, Greg A.; Beaulieu, Nicole M.; LeMay, Steven G.; Nelson, Dwayne R.; Palchetti, Johnny; Benbrahim, Jamal, Decoupling of the graphical presentation of a game from the presentation logic.
  12. Dykes, John W.; Blankenhagen, Tony R.; Mosley, William D., Disc storage system employing non-volatile magnetoresistive random access memory.
  13. Suijin Taketa JP; Yuuichi Tarouda JP; Tatsuhiko Machida JP; Sawao Iwatani JP; Keiichi Yorimitsu JP; Sanae Kamakura JP; Satoshi Yazawa JP; Takuya Kurihara JP; Yasuyoshi Sugesawa JP, Disk array device.
  14. Hayashi,Katsunori, Disk array device and battery output control method for disk array device.
  15. Morita, Hirofumi; Ishida, Takashi, Disk array device including a memory with backup power supply and method thereof.
  16. Koh, Kian Kiat, Energy storage method and system to power functional safety diagnostic subsystem.
  17. Killian, Daniel E.; Bodmann, Douglas R.; Terdan, Dale R.; Schultz, Ronald E.; Kay, James J., Energy storage module.
  18. Sprouse, Steven T.; Parikh, Dhaval; Kapoor, Arjun, Enhanced write abort mechanism for non-volatile memory.
  19. LeMay, Steven G.; Nelson, Dwayne R.; Breckner, Robert E.; Schlottmann, Greg A.; Beaulieu, Nicole M.; Palchetti, Johnny; Benbrahim, Jamal, Game development architecture that decouples the game logic from the graphics logic.
  20. LeMay, Steven G.; Nelson, Dwayne R.; Breckner, Robert E.; Schlottmann, Greg A.; Beaulieu, Nicole M.; Palchetti, Johnny; Benbrahim, Jamal, Game development architecture that decouples the game logic from the graphics logic.
  21. Dawkins, George John; Desai, Prakash Vinodrai; McIntosh, Gordon D.; Patel, Kanisha, Handling multiple operating system capabilities in a logical partition data processing system.
  22. Yoshida, Osamu, Information recording device and information recording method.
  23. Kano, Azuma; Sato, Masahiko, Information storage apparatus including an uninterruptible power supply (UPS) and an interlock control method of the same.
  24. Kano,Azuma; Sato,Masahiko, Information storage apparatus including an uninterruptible power supply (UPS) and an interlock control method of the same.
  25. Azuma Kano JP; Masahiko Sato JP, Information storage apparatus including an uniterruptible power supply (UPS) and an interlock control method of the same, comprising.
  26. Boggs, Gary Lee, Interrupted write protection with generic storage.
  27. Cockerille, Warner R.; Chen, Xuedong; Quraishi, Nadeem A.; Schlottmann, Gregory A., Magnetoresistive memory units as read only memory devices in gaming machines.
  28. Ryu, Chang-hyun, Method and apparatus for controlling power of computer system using wake up LAN (local area network) signal.
  29. Fukumori,Mitsuo; Suzuki,Hiroshi; Matsushige,Hiromi; Ogawa,Masato; Yokoyama,Tomokazu, Method for backing up power supply of disk array device and system thereof.
  30. Hsu, Hsien-Yueh; Shiu, Long-Loon, Method for suspending, resuming, and turning on a computer system without being affected by an abnormal power failure.
  31. Gordon, Raz, Method of controlling volatile memory and system thereof.
  32. Dunstan, Robert A., Operational state preservation in the absence of AC power.
  33. Rowe, Richard E.; Moser, Timothy W.; Schaefer, Craig Michael; Iddings, Cara; Nelson, Dwayne R., Pluggable modular gaming modifiers and configuration templates for gaming environments.
  34. Kern, Wiliam; Hsueh, Chih; Hou, Ping, Power safe translation table operation in flash memory.
  35. Hammond,Brad T.; Redmond,Daniel J.; Collemer,Jeffrey B.; Giaquinto,Todd J.; L'Heureux,Diane M., Power supply critical state monitoring system.
  36. Kakihara, Koji, Recovery of duplex data system after power failure.
  37. Costa, Pier Ugo; Zaccheroni, Donatella; Mistroni, Paolo, Techniques for communicating data amongst controllers in a power supply system.
  38. Gaertner, Mark Allen; Trantham, Jon; Krishnamurthy, Vidya; Faulhaber, Steve; Yang, Yong, Torn write mitigation.
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