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Disk drive with cache controlled adaptively for amount of prefetch 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-012/08
출원번호 US-0884281 (1997-06-26)
발명자 / 주소
  • Sokolov Daniel John
  • Swatosh Timothy
출원인 / 주소
  • Western Digital Corporation
대리인 / 주소
    Young
인용정보 피인용 횟수 : 52  인용 특허 : 4

초록

A method of operating a disk drive having a cache provides for adapting the amount of prefetch. The drive also has an intelligent interface for communicating with a host, and a magnetic disk. The cache is divisible into a number of segments, and employs a cache control structure including a cache ar

대표청구항

[ We claim:] [1.] In a disk drive having an intelligent interface for communicating with a host, a magnetic disk, and a cache wherein the cache is divisible into a number of segments, wherein the cache employs a cache control structure including a cache array with a cache array entry, wherein the di

이 특허에 인용된 특허 (4)

  1. Kranich Uwe,DEX, Apparatus and method for reducing read miss latency by predicting sequential instruction read-aheads.
  2. Jeffries Kenneth L. (15807 Booth Cir. Leander TX 78641) Jones Craig S. (12015 Scribe Dr. Austin TX 78759), Disk drive array with request fragmentation.
  3. Ng Spencer W.-F. (San Jose CA), Method and apparatus for adaptive circular predictive buffer management.
  4. Yanai Moshe (Framingham MA) Vishlitzky Natan (Brookline MA) Alterescu Bruno (Newton MA) Castel Daniel (Framingham MA), System and method for dynamically controlling cache management.

이 특허를 인용한 특허 (52)

  1. Ravi Kumar Arimilli ; Lakshminarayana Baba Arimilli ; Leo James Clark ; John Steven Dodson ; Guy Lynn Guthrie ; James Stephen Fields, Jr., Cache allocation policy based on speculative request history.
  2. Hooker, Rodney E.; Reed, Douglas R.; Greer, John Michael; Eddy, Colin, Cache memory budgeted by chunks based on memory access type.
  3. Hooker, Rodney E.; Reed, Douglas R.; Greer, John Michael; Eddy, Colin, Cache memory budgeted by ways based on memory access type.
  4. Hooker, Rodney E.; Reed, Douglas R.; Greer, John Michael; Eddy, Colin; Parks, Terry, Cache replacement policy that considers memory access type.
  5. Gara, Alan G.; Chen, Dong; Heidelberger, Philip; Ohmacht, Martin, Combined group ECC protection and subgroup parity protection.
  6. Gara, Alan; Chen, Dong; Heidelberger, Philip; Ohmacht, Martin, Combined group ECC protection and subgroup parity protection.
  7. Gara, Alan; Chen, Dong; Heidelberger, Philip; Ohmacht, Martin, Combined group ECC protection and subgroup parity protection.
  8. Chen, Dong; Gara, Alan G.; Giampapa, Mark E.; Heidelberger, Philip; Steinmacher-Burow, Burkhard; Vranas, Pavlos, DMA engine for repeating communication patterns.
  9. Gara, Alan G.; Marcella, James A.; Ohmacht, Martin, Data eye monitor method and apparatus.
  10. Wang, Ming Y.; Thelin, Gregory B., Disk drive adjusting read-ahead to optimize cache memory allocation.
  11. Atai-Azimi, Alireza, Disk drive allocating cache segments by mapping bits of a command size into corresponding segment pools.
  12. Wang, Ming Y., Disk drive employing thresholds for cache memory allocation.
  13. Thelin, Gregory B.; Wang, Ming Y., Disk drive maintaining a cache link attribute for each of a plurality of allocation states.
  14. Huynh, Sang, Disk drive to coalesce unaligned writes in write operations.
  15. Gara, Alan G.; Chen, Dong; Coteus, Paul W.; Flynn, William T.; Marcella, James A.; Takken, Todd; Trager, Barry M.; Winograd, Shmuel, Error correcting code with chip kill capability and power saving enhancement.
  16. Ravi Kumar Arimilli ; Lakshminarayana Baba Arimilli ; Leo James Clark ; John Steven Dodson ; Guy Lynn Guthrie ; James Stephen Fields, Jr., Extended cache state with prefetched stream ID information.
  17. Chen, Dong; Gara, Alan; Heidelberger, Philip; Ohmacht, Martin; Vranas, Pavlos, Extended write combining using a write continuation hint flag.
  18. Neufeld, E. David; Frantz, Christopher J., Fast disk cache writing system.
  19. Hooker, Rodney E.; Reed, Douglas R.; Greer, John Michael; Eddy, Colin; Loper, Albert J., Fully associative cache memory budgeted by memory access type.
  20. Chen, Dong; Heidelberger, Phillip; Vranas, Pavlos, Hardware packet pacing using a DMA in a parallel computer.
  21. Ravi Kumar Arimilli ; Lakshminarayana Baba Arimilli ; Leo James Clark ; John Steven Dodson ; Guy Lynn Guthrie ; James Stephen Fields, Jr., Layered speculative request unit with instruction optimized and storage hierarchy optimized partitions.
  22. Arimilli, Ravi Kumar; Arimilli, Lakshminarayana Baba; Clark, Leo James; Dodson, John Steven; Guthrie, Guy Lynn; Fields, Jr., James Stephen, Mechanism for high performance transfer of speculative request data between levels of cache hierarchy.
  23. Almasi, Gheorghe; Dozsa, Gabor; Kumar, Sameer, Mechanism to support generic collective communication across a variety of programming models.
  24. Blocksome, Michael; Chen, Dong; Giampapa, Mark E.; Heidelberger, Philip; Kumar, Sameer; Parker, Jeffrey J., Message passing with a limited number of DMA byte counters.
  25. Blumrich, Matthias A.; Chen, Dong; Gara, Alan G.; Giampapa, Mark E.; Heidelberger, Philip; Ohmacht, Martin; Salapura, Valentina; Vranas, Pavlos, Method and apparatus for efficiently tracking queue entries relative to a timestamp.
  26. O'Neil John T. ; Israel Ben, Method and apparatus for enhancing the disk cache process by dynamically sizing prefetch data associated with read requests based upon the current cache hit rate.
  27. Blumrich, Matthias A.; Salapura, Valentina, Method and apparatus for single-stepping coherence events in a multiprocessor system under software control.
  28. Gara, Alan; Ohmacht, Martin; Salapura, Valentina; Sugavanam, Krishnan; Hoenicke, Dirk, Method and apparatus of prefetching streams of varying prefetch depth.
  29. Bellofatto, Ralph E.; Ellavsky, Matthew R.; Gara, Alan G.; Giampapa, Mark E.; Gooding, Thomas M.; Haring, Rudolf A.; Hehenberger, Lance G.; Ohmacht, Martin, Method and apparatus to debug an integrated circuit chip via synchronous clock stop and scan.
  30. Osborne, Randy B.; Creta, Kenneth C.; Bennett, Joseph A.; Ajanovic, Jasmin, Method and system to improve prefetching operations.
  31. Ravi Kumar Arimilli ; Lakshminarayana Baba Arimilli ; Leo James Clark ; John Steven Dodson ; Guy Lynn Guthrie ; James Stephen Fields, Jr., Method for instruction extensions for a tightly coupled speculative request unit.
  32. Shatil, Arod; Epstein, Edith L.; Ludlum, Stephen A., Methods and apparatus for providing host controlled caching of data in a storage system.
  33. Klein, Dean A., Non-volatile hard disk drive cache system and method.
  34. Klein, Dean A., Non-volatile hard disk drive cache system and method.
  35. Ahmadi-Ardakani, Arya, Optimized N-stream sequential media playback caching method and system.
  36. Ravi Kumar Arimilli ; Lakshminarayana Baba Arimilli ; Leo James Clark ; John Steven Dodson ; Guy Lynn Guthrie ; James Stephen Fields, Jr., Optimized cache allocation algorithm for multiple speculative requests.
  37. Chen, Dong; Gabor, Dozsa; Giampapa, Mark E.; Heidelberger, Phillip, Optimized collectives using a DMA on a parallel computer.
  38. Maroney, John E.; Le, Hai, Power conservation based on caching.
  39. Harvey,David W., Pre-fetch prediction method for disk drives.
  40. Lakshmi Rao ; James T. Battle, Prefetch buffer with continue detect.
  41. Blumrich, Matthias A.; Salapura, Valentina, Programmable partitioning for high-performance coherence domains in a multiprocessor system.
  42. Hooker, Rodney E.; Reed, Douglas R.; Greer, John Michael; Eddy, Colin, Set associative cache memory with heterogeneous replacement policy.
  43. Chiu, George; Gara, Alan G.; Salapura, Valentina, Shared performance monitor in a multiprocessor system.
  44. Chiu, George; Gara, Alan G.; Salapura, Valentina, Shared performance monitor in a multiprocessor system.
  45. Ryan, Kevin J.; Johnson, Christopher S., Synchronous DRAM with selectable internal prefetch size.
  46. Ryan, Kevin J.; Johnson, Christopher S., Synchronous DRAM with selectable internal prefetch size.
  47. Ryan,Kevin J.; Johnson,Christopher S., Synchronous DRAM with selectable internal prefetch size.
  48. Derbeko, Philip; Don, Arieh; Eyal, Anat; Veprinsky, Alex; Benhanokh, Zvi Gabriel, System and method for data prediction.
  49. Blumrich, Matthias A.; Chen, Dong; Gara, Alan G.; Giampapa, Mark E.; Hoenicke, Dirk; Ohmacht, Martin; Salapura, Valentina; Sugavanam, Krishnan, System and method for programmable bank selection for banked memory subsystems.
  50. Hakura,Ziyad S.; Langendorf,Brian Keith; Pescador,Stefano A.; Danilak,Radoslav; Simeral,Brad W., System, apparatus and method for predicting accesses to a memory.
  51. Dutta, Rabindranath, System, method, and program for balancing cache space requirements with retrieval access time for large documents on the internet.
  52. Arimilli, Ravi Kumar; Arimilli, Lakshminarayana Baba; Clark, Leo James; Dodson, John Steven; Guthrie, Guy Lynn; Fields, Jr., James Stephen, Time based mechanism for cached speculative data deallocation.
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