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Process for converting a wire bond pad to a flip chip solder bump pad and pad formed thereby 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
  • H01L-021/48
  • H01L-021/50
출원번호 US-0883694 (1997-06-27)
발명자 / 주소
  • Erickson Curt A
출원인 / 주소
  • Delco Electronics Corporation
대리인 / 주소
    Funke
인용정보 피인용 횟수 : 36  인용 특허 : 6

초록

A method for forming a solder bump pad (22), and more particularly converting a wire bond pad (12) of a surface-mount IC device (10) to a flip chip solder bump pad (22), such that the IC device (10) can be flip-chip mounted to a substrate. The process generally entails an aluminum wire bond pad (12)

대표청구항

[ What is claimed is:] [1.] A method for forming a solder bump pad, the method comprising the steps of:providing an aluminum pad on a substrate, at least a portion of the aluminum pad being exposed through a dielectric layer on the substrate;depositing a nickel layer on the portion of the aluminum p

이 특허에 인용된 특허 (6)

  1. Agarwala Birendra N. (Hopewell Junction NY) Datta Madhav (Yorktown Heights NY) Gegenwarth Richard E. (Poughkeepsie NY) Jahnes Christopher V. (Monsey NY) Miller Patrick M. (Poughkeepsie NY) Nye ; III , Etching processes for avoiding edge stress in semiconductor chip solder bumps.
  2. Chiu George W. (Palo Alto CA), Method and apparatus for forming solder balls and solder columns.
  3. Dishon Giora J. (Chapel Hill NC), Method of building solder bumps.
  4. Lochon Henri (Saintry-sur-Seine FRX) Robert Georges (La Ferte-Alais FRX), Method of forming metal contact pads and terminals on semiconductor chips.
  5. Agarwala Birendra N. (Hopewell Junction NY), Process of making pad structure for solder ball limiting metallurgy having reduced edge stress.
  6. Oishi Akira (Tokyo JPX) Usui Toshio (Tokyo JPX) Teshima Hidekazu (Tokyo JPX) Morishita Tadataka (Tokyo JPX), Substrate material for the preparation of oxide superconductors.

이 특허를 인용한 특허 (36)

  1. Patel Sunil A. ; Chia Chok J. ; Desai Kishor V., Apparatus and method for improving ball joints in semiconductor packages.
  2. Seshan, Krishan, Ball limiting metallurgy for input/outputs and methods of fabrication.
  3. Seshan, Krishna, Ball limiting metallurgy for input/outputs and methods of fabrication.
  4. Hua,Fay; Wu,Albert T.; Jeng,Kevin; Seshan,Krishna, Ball-limiting metallurgies, solder bump compositions used therewith, packages assembled thereby, and methods of assembling same.
  5. Jan, Jong Rong; Lu, Tsai Hua; Chiu, Sao Ling; Kung, Ling Chen, Electronic devices including offset conductive bumps.
  6. Nair, Krishna K.; Rinne, Glenn A.; Batchelor, William E., Electronic structures including conductive layers comprising copper and having a thickness of at least 0.5 micrometers.
  7. Lim,Victor Seng Keong; Zhang,Fan; Lam,Jeffrey, Elevated bond-pad structure for high-density flip-clip packaging and a method of fabricating the structures.
  8. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Low fabrication cost, fine pitch and high reliability solder bump.
  9. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Low fabrication cost, fine pitch and high reliability solder bump.
  10. Rinne,Glenn A.; Nair,Krishna K., Low temperature methods of bonding components and related structures.
  11. Kwok Keung Paul Ho SG; Simon Chooi SG; Yi Xu SG; Yakub Aliyu SG; Mei Sheng Zhou SG; John Leonard Sudijono SG; Subhash Gupta SG; Sudipto Ranendra Roy SG, Method of application of conductive cap-layer in flip-chip, COB, and micro metal bonding.
  12. Ho, Kwok Keung Paul; Chooi, Simon; Xu, Yi; Aliyu, Yakub; Zhou, Mei Sheng; Sudijono, John Leonard; Gupta, Subhash; Roy, Sudipto Ranendra, Method of application of conductive cap-layer in flip-chip, cob, and micro metal bonding.
  13. Kwok Keung Paul Ho SG; Yi Xu SG; Simon Chooi SG; Yakub Aliyu SG; Mei Sheng Zhou SG; John Leonard Sudijono SG; Subhash Gupta SG; Sudipto Ranendra Roy SG, Method of application of displacement reaction to form a conductive cap layer for flip-chip, COB, and micro metal bonding.
  14. Aliyu, Yakub; Chooi, Simon; Zhou, Meisheng; Sudijono, John; Gupta, Subhash; Roy, Sudipto Ranendra, Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding.
  15. Chooi, Simon; Aliyu, Yakub; Zhou, Mei Sheng; Sudijono, John; Gupta, Subhash; Roy, Sudipto; Ho, Paul; Xu, Yi, Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding.
  16. Chooi,Simon; Aliyu,Yakub; Zhou,Mei Sheng; Sudijono,John; Gupta,Subhash; Roy,Sudipto; Ho,Paul; Xu,Yi, Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding.
  17. Chooi,Simon; Aliyu,Yakub; Zhou,Mei Sheng; Sudijono,John; Gupta,Subhash; Roy,Sudipto; Ho,Paul; Yi,Xu, Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding.
  18. Simon Chooi SG; Yakub Aliyu SG; Mei Sheng Zhou SG; John Sudijono SG; Subhash Gupta SG; Sudipto Ranendra Roy SG; Paul Ho SG; Xu Yi SG, Method of fabricating copper metal bumps for flip-chip or chip-on-board IC bonding on terminating copper pads.
  19. Nair, Krishna K.; Rinne, Glenn A.; Batchelor, William E., Methods of forming electronic structures including conductive shunt layers and related structures.
  20. Mis, J. Daniel; Adema, Gretchen; Bumgarner, Susan; Chilukuri, Pooja; Rinne, Christine; Rinne, Glenn, Methods of forming lead free solder bumps.
  21. Mis,J. Daniel, Methods of forming solder bumps on exposed metal pads.
  22. Jan,Jong Rong; Lu,Tsai Hua; Chiu,Sao Ling; Kung,Ling Chen, Methods of selectively bumping integrated circuit substrates and related structures.
  23. Brunner, Sebastian; Kaul, Franz; Fischer, Annette, Module substrate and production method.
  24. Batchelor, William E.; Rinne, Glenn A., Non-Circular via holes for bumping pads and related structures.
  25. Rinne,Glenn A., Optical structures including liquid bumps and related methods.
  26. Huang, Ching-Cheng; Lin, Chuen-Jye; Lei, Ming-Ta; Lin, Mou-Shiung, Reliable metal bumps on top of I/O pads after removal of test probe marks.
  27. Nakata, Yosuke; Tarutani, Masayoshi, Semiconductor device and semiconductor device manufacturing method.
  28. Nakata, Yosuke; Tarutani, Masayoshi, Semiconductor device and semiconductor device manufacturing method.
  29. Aiba, Yoshitaka; Sato, Mitsutaka, Semiconductor device manufacturing method having a step of applying a copper foil on a substrate as a part of a wiring connecting an electrode pad to a mounting terminal.
  30. Gridelet, Evelyne; Widdershoven, Franciscus; Garcia Tello, Pablo; Lambert, Magali, Sensor chip and method of manufacturing the same.
  31. Bachman, Mark A.; Osenbach, John W.; Desai, Kishor V., Solder interconnect by addition of copper.
  32. Bachman, Mark A.; Osenbach, John W.; Desai, Kishor V., Solder interconnect by addition of copper.
  33. Mis, J. Daniel; Adema, Gretchen; Bumgarner, Susan; Chilukuri, Pooja; Rinne, Christine; Rinne, Glenn, Solder structures including barrier layers with nickel and/or copper.
  34. Suh, Daewoong, Solders with intermetallic phases, solder bumps made thereof, packages containing same, and methods of assembling packages therewith.
  35. Akram, Salman; Wood, Alan G., Under bump metalization pad and solder bump connections.
  36. Akram,Salman; Wood,Alan G., Under bump metallization pad and solder bump connections.
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