초록 ▼

A programmable gate array (FPGA) comprises a CPU coupled to a configuration memory array. Bitstream data used for configuring the configuration memory array is encoded to combine programming instructions and configuration data. The CPU receives and decodes the encoded bitstream data, and executes th

A programmable gate array (FPGA) comprises a CPU coupled to a configuration memory array. Bitstream data used for configuring the configuration memory array is encoded to combine programming instructions and configuration data. The CPU receives and decodes the encoded bitstream data, and executes the programming instructions to efficiently load configuration data into the configuration memory array. For instance, configuration data can be temporarily stored in the CPU and reused where data patterns in the configuration memory array repeat. Use of the programmable CPU for loading the configuration memory array reduces the amount of data transmitted to the FPGA during array configuration.

대표청구항 ▼

[ What is claimed is:] [23.] A method for configuring the configuration memory array of a field programmable gate array (FPGA), the method comprising the steps:encoding gate array configuration data with programming instructions to produce encoded bitstream data;transferring bitstream data to the FP

[ What is claimed is:] [23.] A method for configuring the configuration memory array of a field programmable gate array (FPGA), the method comprising the steps:encoding gate array configuration data with programming instructions to produce encoded bitstream data;transferring bitstream data to the FPGA;receiving the bitstream data into a CPU on the FPGA;decoding the bitstream data to a separate the programming instructions from the configuration data; andperforming arithmetic functions to configure the FPGA in response to programming instructions in the bitstream.