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Capped copper electrical interconnects 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
출원번호 US-0950262 (1997-10-14)
발명자 / 주소
  • Farooq Mukta Shaji
  • Kaja Suryanarayana
  • Perfecto Eric Daniel
  • White George Eugene
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Ahsan
인용정보 피인용 횟수 : 48  인용 특허 : 10

초록

The present invention relates generally to a new structure and method for capped copper electrical interconnects. More particularly, the invention encompasses a novel structure in which one or more of the copper electrical interconnects within a semiconductor substrate are capped to obtain a robust

대표청구항

[ What is claimed is:] [1.] A capped electrical interconnect structure comprising a substrate, having at least one first seed layer, at least one second seed layer over said at least one first seed layer, a copper material on a portion of said at least one second seed layer and at least one capping

이 특허에 인용된 특허 (10)

  1. Farooq Mukta S. (Hopewell Junction NY) Kaja Suryanarayana (Hopewell Junction NY) Perfecto Eric D. (Poughkeepsie NY) White George E. (Hoffman Estates IL), Capped copper electrical interconnects.
  2. Farooq Mukta Shaji ; Kaja Suryanarayana ; Perfecto Eric Daniel ; White George Eugene, Capped copper electrical interconnects.
  3. Ueno Hiroshi (Tokyo JPX), Electrode structure for a semiconductor device.
  4. Rapoport Nahum (Canton MA) Curley Michael (S. Lawrence MA), High-density multilayer interconnection system on a ceramic substrate for high current applications and method of manufa.
  5. Schreiber Christopher M. (Newport Beach CA) Feigenbaum Haim (Irvine CA), Method for electrodepositing corrosion barrier on isolated circuitry.
  6. Pan Ju-Don T. (Austin TX), Method of making an electrical multilayer copper interconnect.
  7. Pan Ju-Don T. (Austin TX), Method of making an electrical multilayer interconnect.
  8. Brighton Jeffrey E. (Katy TX) Roane Bobby A. (Manuel TX), Methods for and products having self-aligned conductive pillars on interconnects.
  9. Kaja Suryanarayana (Hopewell Junction NY) O\Sullivan Eugene J. (Nyack NY) Schrott Alejandro G. (New York NY), Process for fabricating improved multilayer interconnect systems.
  10. Hall R. Dean (Baltimore MD), Tin and gold plating process.

이 특허를 인용한 특허 (48)

  1. Li,Shijian; Chen,Llang Yuh; Duboust,Alain, Articles for polishing semiconductor substrates.
  2. O'Brien,Kevin P.; Brask,Justin K., Capping of copper structures in hydrophobic ILD using aqueous electro-less bath.
  3. Yakobson,Eric; Hurtubise,Richard; Witt,Christian; Chen,Qingyun, Capping of metal interconnects in integrated circuit electronic devices.
  4. Yakobson,Eric; Hurtubise,Richard; Witt,Christian; Chen,Qingyun, Capping of metal interconnects in integrated circuit electronic devices.
  5. Lin, Mou-Shiung; Lin, I, Shih-Hsiung, Chip package having a chip combined with a substrate via a copper pillar.
  6. Chen, Ke-Hung; Lin, Shih-Hsiung; Lin, Mou-Shiung, Chip package with dam bar restricting flow of underfill.
  7. Chopra, Dinesh; Fishburn, Fred, Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby.
  8. Chopra, Dinesh; Fishburn, Fred, Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby.
  9. Chopra,Dinesh; Fishburn,Fred, Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby.
  10. Chopra,Dinesh; Fishburn,Fred, Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby.
  11. Chopra,Dinesh; Fishburn,Fred, Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby.
  12. Lee, Jin-Yuan; Chou, Chien-Kang; Lin, Shih-Hsiung; Kuo, Hsi-Shan, Cylindrical bonding structure and method of manufacture.
  13. Hua,Fay, Electromigration barrier layers for solder joints.
  14. Hua,Fay, Electromigration barrier layers for solder joints.
  15. Cohen, Uri, Electroplated metallic conductors.
  16. Cohen, Uri, High speed electroplating metallic conductors.
  17. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Low fabrication cost, fine pitch and high reliability solder bump.
  18. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Low fabrication cost, fine pitch and high reliability solder bump.
  19. Lee, Jin-Yuan; Lei, Ming-Ta; Huang, Ching-Cheng; Lin, Chuen-Jye, Low fabrication cost, high performance, high reliability chip scale package.
  20. Lee, Jin-Yuan; Lei, Ming-Ta; Huang, Ching-Cheng; Lin, Chuen-Jye, Low fabrication cost, high performance, high reliability chip scale package.
  21. Lee, Jin-Yuan; Lei, Ming-Ta; Huang, Ching-Cheng; Lin, Chuen-Jye, Low fabrication cost, high performance, high reliability chip scale package.
  22. Lin, Mou-Shiung, Metallization structure over passivation layer for IC chip.
  23. Gao, Guohua, Method and structure for wafer-level packaging.
  24. Gao, Guohua, Method and structure for wafer-level packaging.
  25. Lee, Jin-Yuan; Chou, Chien-Kang; Lin, Shih-Hsiung; Kuo, Hsi-Shan, Method for fabricating circuit component.
  26. Abe, Shinji; Kawasaki, Kazushige, Method for manufacturing semiconductor optical device.
  27. Chen Sheng-Hsiung,TWX ; Tsai Ming-Hsing,TWX, Method for preventing seed layer oxidation for high aspect gap fill.
  28. Takewaki, Toshiyuki; Ueno, Kazuyoshi, Method of forming a semiconductor device featuring copper wiring layers of different widths having metal capping layers of different thicknesses formed thereon.
  29. Lin, Shih-Hsiung; Lin, Mou-Shiung, Method of joining chips utilizing copper pillar.
  30. Lin, Shih-Hsiung; Lin, Mou-Shiung, Method of joining chips utilizing copper pillar.
  31. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  32. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  33. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  34. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  35. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  36. Lee, Jin-Yuan; Chen, Ying-chih, Method of wire bonding over active area of a semiconductor circuit.
  37. Chan, Lap; Li, Sam Fong Yau; Ng, Hou Tee, Method to encapsulate copper plug for interconnect metallization.
  38. Shang, Quanyuan; White, John M.; Bachrach, Robert Z.; Law, Kam S., Methods to form metal lines using selective electrochemical deposition.
  39. Christy Mei-Chu Woo ; Minh Quoc Tran, Pre-fill CMP and electroplating method for integrated circuits.
  40. Vivian W. Ryan, Process for fabricating copper interconnect for ULSI integrated circuits.
  41. Huang, Ching-Cheng; Lin, Chuen-Jye; Lei, Ming-Ta; Lin, Mou-Shiung, Reliable metal bumps on top of I/O pads after removal of test probe marks.
  42. Chou, You-Hua; Hong, Min Hao; Tsai, Jian-Shin; Liao, Miao-Cheng; Hsiang Ko, Hsiang, Reverse damascene process.
  43. Chou, You-Hua; Hong, Min Hao; Tsai, Jian-Shin; Liao, Miao-Cheng; Hsiang Ko, Hsiang, Reverse damascene process.
  44. Chou, You-Hua; Hong, Min Hao; Tsai, Jian-Shin; Liao, Miao-Cheng; Hsiang Ko, Hsiang, Reverse damascene process.
  45. Takewaki,Toshiyuki; Ueno,Kazuyoshi, Semiconductor device featuring copper wiring layers of different widths having metal capping layers of different thickness formed thereon, and method for manufacturing the same.
  46. Lin, Mou-Shiung, Solder interconnect on IC chip.
  47. Lin, Mou-Shiung; Lei, Ming-Ta; Lin, Chuen-Jye, Structure and manufacturing method of a chip scale package.
  48. Woo, Christy Mei-Chu; Wang, Connie Pin-Chin; Avanzino, Steve C., Utilization of annealing enhanced or repaired seed layer to improve copper interconnect reliability.
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