초록 ▼

A power-up circuit in a computer system drives a memory device such as a dynamic random access memory (DRAM) to an initial condition after the computer system is turned on or reset. The power-up circuit also advantageously drives the memory device into the initial condition upon detecting a transien

A power-up circuit in a computer system drives a memory device such as a dynamic random access memory (DRAM) to an initial condition after the computer system is turned on or reset. The power-up circuit also advantageously drives the memory device into the initial condition upon detecting a transient such as a negative glitch in a supply voltage being provided to the memory device. The power-up circuit includes a voltage level detector which causes a power-up signal to be provided to the memory device upon detecting that the supply voltage is less than a threshold voltage of the memory device which is necessary for the memory device to operate in an operational state. The power-up circuit also includes a delay circuit which causes the power-up signal to be provided to the memory device upon detecting that the supply voltage is beginning to rise from a quiescent voltage and at least until an amount of time determined by an RC time constant of the memory device for the memory device to enter the initial condition has passed. In response to receiving the power-up signal, the memory device enters the initial condition.

대표청구항 ▼

[ We claim:] [30.] A dynamic random-access memory chip comprising:a dynamic random-access memory circuit, the dynamic random-access memory circuit being constructed to respond to a memory reset signal by entering an initial condition and to operate in an operational state in the absence of the power

[ We claim:] [30.] A dynamic random-access memory chip comprising:a dynamic random-access memory circuit, the dynamic random-access memory circuit being constructed to respond to a memory reset signal by entering an initial condition and to operate in an operational state in the absence of the power-up signal when receiving a supply voltage; anda reset circuit for providing the memory reset signal to the memory device, the reset circuit comprising:a voltage level detector providing a first reset signal in response to detecting that the absolute value of the supply voltage is less than a first voltage;a delay circuit providing a second reset signal for the duration of a delay period after the absolute value of the supply voltage has become greater than a second voltage; anda logic circuit coupled to the voltage level detector and the delay circuit, the logic circuit providing the memory reset signal to the electronic device in response to receiving either of the first and second reset signals.