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Method for forming field effect transistor having multiple gate electrodes surrounding the channel region 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • M01L-021/00
  • M01L-021/336
출원번호 US-0030390 (1998-02-25)
우선권정보 JP-0026270 (1995-01-20)
발명자 / 주소
  • Mukai Mikio,JPX
출원인 / 주소
  • Sony Corporation, JPX
대리인 / 주소
    Hill & Simpson
인용정보 피인용 횟수 : 77  인용 특허 : 9

초록

A field effect transistor comprising source and drain regions, a channel region composed of a semiconductor layer formed between the source and drain regions and gate electrodes disposed to at least three surfaces surrounding the channel region. The structure can increase the number of carriers indu

대표청구항

[ What is claimed is:] [1.] A method of forming a field effect transistor, comprising the steps of:fabricating a protrusion on a semiconductor substrate;forming a thin insulation film on the semiconductor substrate having the protrusion formed thereon;forming a film of an electrode material on said

이 특허에 인용된 특허 (9)

  1. Chang, Chin-An; Chang, Leroy L.; Esaki, Leo; Mendez, Emilio E., FET With heterojunction induced channel.
  2. Kohn Erhard (Orsay FRX), Field effect transistor with a submicron vertical structure and its production process.
  3. Hori Yoshihiro (Yokosuka JPX) Doi Keiichiro (Yokohama JPX) Endo Manabu (Yokohama JPX) Yoshida Toshiki (Yokohama JPX), Field effect transistor with active layer apart from guard-ring.
  4. Khadder Wadie N. (Santa Clara County CA) Vokac James P. (Santa Clara County CA) Dobkin Robert C. (Santa Clara County CA), High speed junction field effect transistor for use in bipolar integrated circuits.
  5. Kumar Mahesh (S. Brunswick Township ; Middlesex County NJ), Microwave frequency power combiner.
  6. Beneking Heinz (Aachen DEX), Semi-conductor arrangement.
  7. Nishizawa Jun-ichi (No. 6-16 ; Komegafukuro 1-chome Sendai-shi ; Miyagi-ken ; 980 JPX) Tamamushi Takashige (Sendai JPX) Motoya Kaoru (Sendai JPX), Semiconductor photoelectric transducer.
  8. Mayer Donald C. (Palos Verdes CA) MacWilliams Kenneth P. (Redondo Beach CA), Silicon-on-insulator gate-all-around MOSFET devices and fabrication methods.
  9. Baba, Yoshiro; Yanagiya, Satoshi; Matsuda, Noburo; Hiraki, Shunichi, Vertical MOSFET having trench covered with multilayer gate film.

이 특허를 인용한 특허 (77)

  1. Kavalieros,Jack T.; Shah,Uday; Rachmady,Willy; Doyle,Brian S., Apparatus and method for selectively recessing spacers on multi-gate devices.
  2. Lindert, Nick; Cea, Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
  3. Doyle, Brian S.; Jin, Been-Yih; Kavalieros, Jack T.; Datta, Suman; Brask, Justin K.; Chau, Robert S., CMOS devices with a single work function gate electrode and method of fabrication.
  4. Brask, Justin K.; Datta, Suman; Doczy, Mark L.; Blackwell, James M.; Metz, Matthew V.; Kavalieros, Jack T.; Chau, Robert S., Dielectric interface for group III-V semiconductor device.
  5. Bryant, Andres; Ieong, Meikei; Muller, K. Paul; Nowak, Edward J.; Fried, David M.; Rankin, Jed, Double gated transistor and method of fabrication.
  6. Bryant,Andres; Ieong,Meikei; Muller,K. Paul; Nowak,Edward J.; Fried,David M.; Rankin,Jed, Double gated transistor and method of fabrication.
  7. Bryant, Andres; Ieong, Meikei; Muller, K. Paul; Nowak, Edward J.; Fried, David M.; Rankin, Jed, Double gated vertical transistor with different first and second gate materials.
  8. Kavalieros, Jack T.; Mukherjee, Niloy; Dewey, Gilbert; Somasekhar, Dinesh; Doyle, Brian S., Embedded memory cell and method of manufacturing same.
  9. Radosavljevic, Marko; Datta, Suman; Doyle, Brian S.; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Majumdar, Amian; Chau, Robert S., Field effect transistor with metal source/drain regions.
  10. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
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  19. Song, Stanley Seungchul; Abu-Rahma, Mohamed Hassan; Han, Beom-Mo, Fin-type device system and method.
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  21. Chenming Hu ; Tsu-Jae King ; Vivek Subramanian ; Leland Chang ; Xuejue Huang ; Yang-Kyu Choi ; Jakub Tadeusz Kedzierski ; Nick Lindert ; Jeffrey Bokor ; Wen-Chin Lee, Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture.
  22. Ervin, Joseph E.; Thornton, Trevor John, Horizontally depleted metal semiconductor field effect transistor.
  23. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors.
  24. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
  25. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
  26. Chang, Peter L. D., Integration of planar and tri-gate devices on the same substrate.
  27. Chang,Peter L. D., Integration of planar and tri-gate devices on the same substrate.
  28. Datta,Suman; Doyle,Brian S.; Chau,Robert S.; Kavalieros,Jack; Zheng,Bo; Hareland,Scott A., Method and apparatus for improving stability of a 6T CMOS SRAM cell.
  29. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
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  31. Shah,Uday; Doyle,Brian S.; Brask,Justin K.; Chau,Robert S., Method of fabricating a multi-cornered film.
  32. Doyle,Brian S.; Datta,Suman; Kavalieros,Jack T.; Majumdar,Amlan, Method of ion implanting for tri-gate devices.
  33. Nowak,Edward J.; Rainey,BethAnn, Method of making a finFET having suppressed parasitic device characteristics.
  34. Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Chau, Robert S., Method of patterning a film.
  35. Ying Keung Leung HK; Yelehanka Ramachandramurthy Pradeep SG; Jia Zhen Zheng SG; Lap Chan ; Elgin Quek SG; Ravi Sundaresan ; Yang Pan SG; James Yong Meng Lee SG, Method to control the channel length of a vertical transistor by first forming channel using selective epi and source/drain using implantation.
  36. James Yong Meng Lee SG; Ying Keung Leung HK; Yelehanka Ramachandramurthy Pradeep SG; Jia Zhen Zheng SG; Lap Chan ; Elgin Quek SG; Ravi Sundaresan ; Yang Pan SG, Method to form a vertical transistor by selective epitaxial growth and delta doped silicon layers.
  37. Chambers, James Joseph; Visokay, Mark Robert, Methods for fabricating a triple-gate MOSFET transistor.
  38. Brask, Justin K.; Kavalieros, Jack; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S.; Doyle, Brian S., Methods for patterning a semiconductor film.
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  40. Chambers,James Joseph, Multiple-gate MOSFET device with lithography independent silicon body thickness.
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  42. Brask,Justin K.; Kavalieros,Jack T.; Doyle,Brian S.; Chau,Robert S., Non-planar microelectronic device having isolation element to mitigate fringe effects and method to fabricate same.
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  44. Hareland,Scott A.; Chau,Robert S.; Doyle,Brian S.; Datta,Suman; Jin,Been Yih, Nonplanar device with stress incorporation layer and method of fabrication.
  45. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
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  76. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
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