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Method of forming a hemispherical grained silicon on refractory metal nitride 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/8242
출원번호 US-0781510 (1997-01-08)
발명자 / 주소
  • Harshfield Steven T.
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Knobbe, Martens, Olson & Bear, LLP
인용정보 피인용 횟수 : 21  인용 특허 : 31

초록

Disclosed is a method of growing hemispherical grained silicon (HSG silicon) over a conductive seed layer. In a preferred embodiment, a contact window is etched in an insulating layer to expose a circuit node, such as an active area of a substrate or a contact plug leading to an active area. A layer

대표청구항

[ I claim:] [1.] A method of forming a plate of a capacitor in an integrated circuit, the method comprising the steps of:etching a contact window through an insulating layer of the integrated circuit;depositing a metal nitride layer over the insulating layer and into the contact window, the metal ni

이 특허에 인용된 특허 (31)

  1. Sandhu Gurtej S. (Boise ID), Anodized polysilicon layer lower capacitor plate of a dram to increase capacitance.
  2. Lee Young Jong,KRX, Capacitor structure for semiconductor device and method of manufacturing the same.
  3. Fazan Pierre C. (Boise ID) Lee Ruojia R. (Boise ID), DRAM cell having a texturized polysilicon lower capacitor plate for increased capacitance.
  4. Fazan Pierre (Boise ID) Sandhu Gurtej S. (Boise ID), Dram cell in which a silicon-germanium alloy layer having a rough surface morphology is utilized for a capacitive surfac.
  5. Mihara Takashi (Iruma JPX) Yoshimori Hiroyuki (Fujino-machi JPX) Watanabe Hitoshi (Tokyo JPX) McMillan Larry D. (Colorado Springs CO) De Araujo Carlos P. (Colorado Springs CO), Ferroelectric integrated circuit.
  6. Ishigami Takashi (Yokohama JPX) Obata Minoru (Inagi JPX) Kawai Mituo (Yokohama JPX) Satou Michio (Yokohama JPX) Yamanobe Takashi (Yokohama JPX) Maki Toshihiro (Yokohama JPX) Yagi Noriaki (Yokohama JP, Highly purified metal material and sputtering target using the same.
  7. Zahurak John K. ; Lane Richard H., Increased interior volume for integrated memory cell.
  8. Chhabra Navjot (Boise ID) Sandhu Gurtej S. (Boise ID), Metal silicide texturizing technique.
  9. Cho Bok-Won,KRX, Method for fabricating capacitor of semiconductor device using hemispherical grain (HSG) polysilicon.
  10. Watanabe Hirohito (Tokyo JPX) Tatsumi Toru (Tokyo JPX), Method for fabricating polycrystalline silicon having micro roughness on the surface.
  11. Dennison Charles H. (Boise ID) Thakur Randhir P. S. (Boise ID), Method for forming enhanced capacitance stacked capacitor structures using hemi-spherical grain polysilicon.
  12. Lee Young J. (Daejeon-si KRX) Cho Bok W. (Chungcheongbuk-do KRX), Method for forming rugged tungsten film and method for fabricating semiconductor device utilizing the same.
  13. Rajeevakumar Thekkemadathil V. (Scarsdale NY), Method for making a high capacitance multi-level storage node for high density TFT load SRAMS with low soft error rates.
  14. Hayashide Yoshio (Hyogo JPX), Method for manufacturing a capacitor having a rough electrode surface.
  15. Han Ki-man (Kyungki KRX) Hwang Chang-gyu (Seoul KRX) Kang Dug-dong (Kyungki KRX) Choi Young-Jae (Kyungki KRX) Yoon Joo-young (Kyungki KRX), Method for manufacturing a capacitor of a semiconductor device.
  16. Tuan Hsiao-Chin (Hsin-Chu TWX) Chou Hsiang-Ming J. (Hsin-Chu TWX), Method for producing a roughened surface capacitor.
  17. Akram Salman (Boise ID) Turner Charles (Chandler AZ) Laulusa Alan (Boise ID), Method of forming a capacitor.
  18. Kataoka Yuzo (Isehara JPX) Asaba Tetsuo (Odawara JPX) Makino Kenji (Yokohama JPX) Yuzurihara Hiroshi (Isehara JPX) Fujita Kei (Sagamihara JPX) Kamei Seiji (Hiratsuka JPX) Akino Yutaka (Isehara JPX) Y, Method of forming metal pattern including a schottky diode.
  19. Cathey David A. (Boise ID) Tuttle Mark E. (Boise ID) Lowrey Tyler A. (Boise ID), Method of increasing capacitance by surface roughening in semiconductor wafer processing.
  20. Hirota Toshiyuki (Tokyo JPX) Honma Ichirou (Tokyo JPX) Watanabe Hirohito (Tokyo JPX) Zenke Masanobu (Tokyo JPX), Method of making a semiconductor integrated circuit device having a capacitor with a porous surface of an electrode.
  21. Sekine Makoto (Tokyo JPX) Kamiyama Satoshi (Tokyo JPX), Method of manufacturing a semiconductor device.
  22. Tatsumi Toru (Tokyo JPX) Sakai Akira (Tokyo JPX), Method of manufacturing polysilicon film including recrystallization of an amorphous film.
  23. Sandhu, Gurtej S.; Doan, Trung T., Method of providing a silicon film having a roughened outer surface.
  24. Thakur Randhir P. S. (Boise ID), Method to prepare hemi-spherical grain (HSG) silicon using a fluorine based gas mixture and high vacuum anneal.
  25. Tuttle Mark E. (Boise ID), Methods for texturizing polysilicon.
  26. Tuttle Mark E. (Boise ID), Methods for texturizing polysilicon utilizing gas phase nucleation.
  27. Brown Kris K. (Garden City ID), Process for fabricating storage capacitor structures using CVD tin on hemispherical grain silicon.
  28. Fazan Pierre (Boise ID) Mathews Viju (Boise ID), Process to manufacture crown stacked capacitor structures with HSG-rugged polysilicon on all sides of the storage node.
  29. Sandhu Gurtej S. (Boise ID) Yu Chang (Boise ID) Liu Yauh-Ching (Boise ID), Semiconductor manufacturing process for decreasing the optical refelctivity of a metal layer.
  30. Lee Ruojia (Boise ID) Gonzalez Fernando (Boise ID), Stacked capacitor doping technique making use of rugged polysilicon.
  31. Wen Duen-Shun (Crompond NY), Textured polysilicon stacked trench capacitor.

이 특허를 인용한 특허 (21)

  1. Gurtej Sandhu ; Garo J. Derderian, ALD method to improve surface coverage.
  2. Sandhu, Gurtej; Derderian, Garo J., ALD method to improve surface coverage.
  3. Cheng Kuo-Hsien,TWX ; Wang Ting-Chun,TWX, Barrier metal composite layer featuring a thin plasma vapor deposited titanium nitride capping layer.
  4. McClure,Brent A.; Kurth,Casey R.; Chen,Shenlin; Gould,Debra K.; Breiner,Lyle D.; Ping,Er Xuan; Fishburn,Fred D.; Wang,Hongmei, Capacitor constructions and methods of forming.
  5. Agarwal,Vishnu K.; Mercaldi,Garry A., Capacitor constructions with enhanced surface area.
  6. Lee, Kee Jeung, Capacitor for semiconductor memory device and method of manufacturing the same.
  7. Lee, Kee Jeung, Capacitor for semiconductor memory device and method of manufacturing the same.
  8. Sandhu, Gurtej; Derderian, Garo J., Film composition.
  9. Lee, Seung-Hwan; Lee, Sang-Hyeop; Kim, Young-Sun; Shim, Se-Jin; Jin, You-Chan; Moon, Ju-Tae; Choi, Jin-Seok; Kim, Young-Min; Kim, Kyung-Hoon; Nam, Kab-Jin; Park, Young-Wook; Won, Seok-Jun; Kim, Young, Integrated circuit capacitors having doped HSG electrodes.
  10. Marsh,Eugene P., Metal layer forming methods and capacitor electrode forming methods.
  11. Sun, Jian; Au, Hing Ho; Phang, Yew Hoong, Method for depositing a very high phosphorus doped silicon oxide film.
  12. Hyung Bok Choi KR, Method for forming capacitor of semiconductor device.
  13. Hyung Bok Choi KR, Method for forming capacitor of semiconductor device.
  14. Yu-Piao Wang TW, Method of fabricating an MOCVD titanium nitride layer utilizing a pulsed plasma treatment to remove impurities.
  15. Yamamoto Ichiro,JPX, Method of manufacturing semiconductor device.
  16. Hyun-bo Shin KR; Myeong-cheol Kim KR; Jin-won Kim KR; Ki-hyun Hwang KR; Jae-young Park KR; Bon-young Koo KR, Methods of forming HSG capacitors from nonuniformly doped amorphous silicon layers and HSG capacitors formed thereby.
  17. Lee, Seung-Hwan; Lee, Sang-Hyeop; Kim, Young-Sun; Shim, Se-Jin; Jin, You-Chan; Moon, Ju-Tae; Choi, Jin-Seok; Kim, Young-Min; Kim, Kyung-Hoon; Nam, Kab-Jin; Park, Young-Wook; Won, Seok-Jun; Kim, Young, Methods of forming integrated circuit capacitors having doped HSG electrodes.
  18. Lee Seung-Hwan,KRX ; Lee Sang-Hyeop,KRX ; Kim Young-Sun,KRX ; Shim Se-Jin,KRX ; Jin You-Chan,KRX ; Moon Ju-Tae,KRX ; Choi Jin-Seok,KRX ; Kim Young-Min,KRX ; Kim Kyung-Hoon,KRX ; Nam Kab-Jin,KRX ; Par, Methods of forming integrated circuit capacitors having improved electrode and dielectric layer characteristics and capacitors formed thereby.
  19. Yu Young-Sub,KRX ; Shin Hyun-Bo,KRX, Methods of forming integrated circuit capacitors having protected layers of HSG silicon therein.
  20. Sandhu, Gurtej; Derderian, Garo J., Semiconductor device with novel film composition.
  21. Sandhu, Gurtej; Derderian, Garo J., Semiconductor device with novel film composition.
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