$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Method and apparatus for reducing particle generation by limiting DC bias spike 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • C23C-016/52
  • H05H-001/46
출원번호 US-0599279 (1996-02-09)
발명자 / 주소
  • Gupta Anand
  • Wolff Stefan
  • Galiano Maria
출원인 / 주소
  • Applied Materials, Inc.
대리인 / 주소
    Townsend & Townsend & Crew
인용정보 피인용 횟수 : 11  인용 특허 : 21

초록

A method and apparatus for preventing particles from dislodging from the interior of a process chamber by preventing DC bias spikes. Such DC bias spikes can be caused by variations in the power or pressure in a process chamber. DC bias spikes are prevented by ramping changes in the pressure at a rat

대표청구항

[ What is claimed is:] [1.] A method for preventing contamination of a substrate by particles in a substrate processing chamber, the method comprising:introducing said substrate into said chamber;flowing processing gases into said chamber;applying an RF field to the chamber to form a plasma; andredu

이 특허에 인용된 특허 (21)

  1. Blackburn Greg ; Kava Joseph ; McGovern Richard ; Rozenzon Yan, Contaminant reduction improvements for plasma etch chambers.
  2. Gupta Anand (San Jose CA) Ye Yan (Campbell CA) Lanucha Joseph (Sunnyvale CA), Control of particle generation within a reaction chamber.
  3. Matsutani Takeshi (Machida JPX), Dry etching method for refractory metals, refractory metal silicides, and other refractory metal compounds.
  4. Egitto Frank D. (Binghamton NY) Mlynko Walter E. (Vestal NY), Enhanced plasma etching.
  5. Moslehi Mehrdad M. (Dallas TX), Low-temperature in-situ dry cleaning process for semiconductor wafers.
  6. Sasaki Naoto (Fuchu JPX) Sato Fumihiko (Fuchu JPX), Magnetron sputtering etching apparatus.
  7. Fukuda Hisashi (Tokyo JPX), Method and device for cleaning substrates.
  8. Blanchard Gary W. (Milton VT) Bossi Charles R. (Burlington VT) Payne Edward H. (Essex Junction VT) Weeks Thomas W. (Essex Junction VT), Method for reducing foreign matter on a wafer etched in a reactive ion etching process.
  9. Gupta Anand (San Jose CA), Method for removing particulate contaminants by magnetic field spiking.
  10. Narita Tomonori (Tokyo JPX), Method of forming conductive layer including removal of native oxide.
  11. Maydan Dan (Los Altos Hills CA) Somekh Sasson (Redwood City CA) Wang David N. (Cupertino CA) Cheng David (San Jose CA) Toshima Masato (San Jose CA) Harari Isaac (Mountain View CA) Hoppe Peter D. (Sun, Multi-chamber integrated process system.
  12. Kinney Patrick (Sunnyvale CA) Fishkin Boris (San Jose CA) Zhao Jun (San Jose CA) Gupta Anand (Santa Clara CA) Bendler Robert (Mountain View CA), Particle monitor system and method.
  13. Savas Stephen E. (Newark CA), Particulate contamination prevention using low power plasma.
  14. Lantsman Alexander D. (Middletown NY), Plasma processing system with reduced particle contamination.
  15. Liao Chih-Cherng (Hsinchu TWX), Plasma purge method for plasma process particle control.
  16. Kawasaki Yoshinao (Yamaguchi JPX) Kawahara Hironobu (Kudamatsu JPX) Kakehi Yutaka (Hikari JPX) Hirobe Kado (Koganei JPX) Kudo Katsuyoshi (Kudamatsu JPX), Plasma treating method and apparatus therefor.
  17. Yoshida Yukimasa (Kawasaki JPX) Watanabe Tohru (Tokyo JPX), Reactive ion etching method.
  18. Gupta Anand (San Jose CA), Reducing particulate contamination during semiconductor device processing.
  19. Gupta Anand (San Jose CA) Lanucha Joseph (San Jose CA), Reducing particulate contamination during semiconductor device processing.
  20. Nulman Jaim (Palo Alto CA), Single anneal step process for forming titanium silicide on semiconductor wafer.
  21. Inoue Minoru (Kawasaki JPX), Sputtering method for fabricating thin film.

이 특허를 인용한 특허 (11)

  1. Kim,Jae Ho; Park,Sang Joon, Chemical vapor deposition method.
  2. Lee, Sangheon; Choi, Dae-Han; Kim, Jisoo; Cirigliano, Peter; Huang, Zhisong; Charatan, Robert; Sadjadi, S. M. Reza, Critical dimension reduction and roughness control.
  3. Lee, Sangheon; Choi, Dae-Han; Kim, Jisoo; Cirigliano, Peter; Huang, Zhisong; Charatan, Robert; Sadjadi, S. M. Reza, Critical dimension reduction and roughness control.
  4. Anand Gupta, Decontamination of a plasma reactor using a plasma after a chamber clean.
  5. Dhas, Arul; Boumatar, Kareem; Ramsayer, Christopher James, Defect control and stability of DC bias in RF plasma-based substrate processing systems using molecular reactive purge gas.
  6. Augustyniak, Edward; Ramsayer, Christopher James; Singhal, Akhil N.; Boumatar, Kareem, Defect control in RF plasma substrate processing systems using DC bias voltage during movement of substrates.
  7. Gat,Arnon, Fast heating and cooling apparatus for semiconductor wafers.
  8. Westerman, Russell; Johnson, David, Method for etching vias.
  9. Kang, Hu; LaVoie, Adrien, Systems and methods for removing particles from a substrate processing chamber using RF plasma cycling and purging.
  10. Kang, Hu; LaVoie, Adrien, Systems and methods for removing particles from a substrate processing chamber using RF plasma cycling and purging.
  11. Sheu, Ben-Li; Dhindsa, Rajinder; Pohray, Vinay; Hudson, Eric A.; Bailey, III, Andrew D., Wiggling control for pseudo-hardmask.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로