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Method of cell placement for an integrated circuit chip comprising chaotic placement and moving windows 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-019/00
출원번호 US-0862791 (1997-05-23)
발명자 / 주소
  • Rostoker Michael D.
  • Koford James S.
  • Jones Edwin R.
  • Boyle Douglas B.
  • Scepanovic Ranko
출원인 / 주소
  • LSI Logic Corporation
대리인 / 주소
    Mitchell, Silberberg & Knupp LLP
인용정보 피인용 횟수 : 39  인용 특허 : 32

초록

In a physical design automation system for producing an optimized cell placement for an integrated circuit chip, a placement optimization methodology is decomposed into a plurality of cell placement optimization processes that are performed simultaneously by parallel processors on input data represe

대표청구항

[ We claim:] [1.] A method of cell placement for an integrated circuit chip, comprising the steps of:(a) computing centroids for a plurality of cells of said placement as a first predetermined function of locations of cells to which said cells are connected respectively;(b) computing first distances

이 특허에 인용된 특허 (32)

  1. Rogers Donald L. (San Jose CA), Apparatus and method for tracking and identifying printed circuit assemblies.
  2. Miki Yoshio (Kokubunji JPX) Suzuki Kei (Kokubunji CA JPX) Takamine Yoshio (Albany CA), Apparatus for wire routing of VLSI.
  3. Hooper Donald F. (Northboro MA) Kundu Snehamay (Marlboro MA), Bitwise implementation mechanism for a circuit design synthesis procedure.
  4. Koford James S. (San Jose CA) Scepanovic Ranko (Cupertino CA) Jones Edwin R. (Sunnyvale CA) Boyle Douglas B. (Palo Alto CA) Rostoker Michael D. (Boulder Creek CA), Cell placement alteration apparatus for integrated circuit chip physical design automation system.
  5. Rostoker Michael D. (Boulder Creek CA) Koford James S. (San Jose CA) Jones Edwin R. (Sunnyvale CA) Boyle Douglas B. (Palo Alto CA) Scepanovic Ranko (Cupertino CA), Computer implemented method for producing optimized cell placement for integrated circiut chip.
  6. Kimmel Milton J. (Somers NY), Configurable parallel pipeline image processing system.
  7. Shaefer Craig G. (Charlestown MA), Genetic algorithm.
  8. Guha Aloke (Minneapolis MN) Harp Steven A. (St. Paul MN) Samad Tariq (Minneapolis MN), Genetic algorithm synthesis of neural networks.
  9. Harvey Robert L. (Lexington MA), Genetic algorithm technique for designing neural networks.
  10. Pryor Richard L. (Voorhees NJ) Cowhig William M. (Philadelphia PA), Hierarchical, computerized design of integrated circuits.
  11. Hong Se J. (Yorktown Heights NY) Nair Ravindra K. (Peekskill NY) Shapiro Eugene (Stamford CT), High speed machine for the physical design of very large scale integrated circuits.
  12. Rostoker Michael D. (Boulder Creek CA) Koford James S. (San Jose CA) Jones Edwin R. (Sunnyvale CA) Boyle Douglas B. (Palo Alto CA) Scepanovic Ranko (Cupertino CA), Integrated circuit physical design automation system utilizing optimization process decomposition and parallel processin.
  13. Chi Mely C. (Murray Hill NJ), Integrated circuits with component placement by rectilinear partitioning.
  14. Linsker Ralph (Scarsdale NY), Iterative method for establishing connections and resulting product.
  15. Kaida Hiromasa (Chiba JPX), Logic cell placement method for semiconductor integrated circuit.
  16. Chene Mon R. (Cupertino CA) Trimberger Stephen M. (San Jose CA), Logic placement using positionally asymmetrical partitioning algorithm.
  17. Cocke John (Bedford Village NY) Malm Richard L. (San Jose CA) Shedletsky John J. (North Salem NY), Logic simulation machine.
  18. Hitchcock ; Sr. Robert B. (Binghamton NY) Graf Matthew C. (Highland NY), Logic simulation machine.
  19. Bischoff Gabriel P. (Marlboro MA) Greenberg Steven S. (Bolton MA), Method and apparatus for circuit simulation using parallel processors including memory arrangements and matrix decomposi.
  20. Date Hiroshi (Hitachi JPX) Hayashi Terumine (Hitachi JPX), Method and apparatus for optimizing element placement and method and apparatus for deciding the optimal element placemen.
  21. Wong Dale M. (San Francisco CA), Method for partitioning of connected circuit components before placement in one or more integrated circuits.
  22. Wong Dale M. (San Francisco CA), Method for placement of circuit components in an integrated circuit.
  23. Antreich Kurt (Germering DEX) Johannes Frank (Germering DEX) Kleinhans Jurgen (Munich DEX) Sigl Georg (Tutzing DEX), Method for placing modules on a carrier.
  24. Finnerty James L. (Lexington MA), Minimizing the interconnection cost of electronically linked objects.
  25. Catlin Gary M. (Cupertino CA), Multiple processor accelerator for logic simulation.
  26. Koza John R. (25372 La Rena La. Los Altos Hills CA 94022), Non-linear genetic algorithms for solving problems by finding a fit composition of functions.
  27. Gelatt ; Jr. Charles D. (Chappaqua NY) Kirkpatrick Edward S. (Croton-on-Hudson NY), Optimization of an organization of many discrete elements.
  28. Boyle Douglas B. (Palo Alto CA) Koford James S. (San Jose CA) Scepanovic Ranko (Cupertino CA) Jones Edwin R. (Sunnyvale CA) Rostoker Michael D. (Boulder Creek CA), Optimization processing for integrated circuit physical design automation system using chaotic fitness improvement metho.
  29. McDermith William O. (Colorado Springs CO) Banki Mehrdad (Colorado Springs CO) Bush Kevin M. (Colorado Springs CO), Partitioning of Boolean logic equations into physical logic devices.
  30. Date Hiroshi (Hitachi) Hayashi Terumine (Hitachi JPX), Placement optimizing method/apparatus and apparatus for designing semiconductor devices.
  31. Wagner Robert A. (Durham NC) Poirier Charles J. (Red Bank NJ), SIMD machine using cube connected cycles network architecture for vector processing.
  32. Toyonaga Masahiko (Osaka JPX) Akino Toshiro (Osaka JPX) Okude Hiroaki (Osaka JPX), System for optimizing a physical organization of elements of an integrated circuit chip through the convergence of a red.

이 특허를 인용한 특허 (39)

  1. Hoffberg, Steven, Agent training sensitive call routing system.
  2. Hoffberg, Steven M., Agent training sensitive call routing system.
  3. Fleischer, Bruce M.; Geiger, David J.; Ngo, Hung C.; Puri, Ruchir; Ren, Haoxing, Automated critical area allocation in a physical synthesized hierarchical design.
  4. Handa, Yujin; Hasegawa, Kei; Iijima, Tomohiro, Data verification method and charged particle beam writing apparatus.
  5. Kuekes Philip J. ; Williams R. Stanley, Demultiplexer for a molecular wire crossbar network (MWCN DEMUX).
  6. Miller, Ronald; Naylor, William C.; Wong, Yiu-Chung, Detailed placer for optimizing high density cell placement in a linear runtime.
  7. Miller,Ronald; Naylor,William C.; Wong,Yiu Chung, Detailed placer for optimizing high density cell placement in a linear runtime.
  8. Miller,Ronald; Naylor,William; Wong,Yiu Chung, Detailed placer for optimizing high density cell placement in a linear runtime.
  9. Griffin, Jed D., Differential amplifier output stage.
  10. Wuidart, Luc; Bardouillet, Michel; Plaza, Laurent, Diversification of a single integrated circuit identifier.
  11. Wuidart,Luc; Bardouillet,Michel; Plaza,Laurent, Generation of a secret quantity based on an identifier of an integrated circuit.
  12. Lee Fung Fung ; Tse John, Hierarchical circuit partitioning using sliding windows.
  13. Qian, Qi-De, Integrated circuits having in-situ constraints.
  14. Kim, Myung-Chul; Ramji, Shyam; Villarrubia, Paul G.; Viswanathan, Natarajan, Large cluster persistence during placement optimization of integrated circuit designs.
  15. Kim, Myung-Chul; Ramji, Shyam; Villarrubia, Paul G.; Viswanathan, Natarajan, Large cluster persistence during placement optimization of integrated circuit designs.
  16. Self, Keith; Urbanski, John, Method and apparatus for encoding a bus to minimize simultaneous switching outputs effect.
  17. Khare, Manoj; Kumar, Akhilesh; Creta, Ken; Looi, Lily P.; George, Robert T.; Cekleov, Michel, Method and apparatus for invalidating a cache line without data return in a multi-node architecture.
  18. Khare, Manoj; Kumar, Akhilesh; Schoinas, Ioannis; Looi, Lily Pao, Method and apparatus for managing transaction requests in a multi-node architecture.
  19. Dotson, Michael W.; DeGroff Drumm, Anthony; Ma, Dazhuang J.; Puri, Ruchir; Trevillyan, Louise H., Method and apparatus for parallel processing of semiconductor chip designs.
  20. Betz, Vaughn; Swartz, Jordan; Gouterman, Vadim, Method and apparatus for performing parallel routing using a multi-threaded routing procedure.
  21. Betz, Vaughn; Swartz, Jordan; Gouterman, Vadim, Method and apparatus for performing parallel routing using a multi-threaded routing procedure.
  22. Betz, Vaughn; Swartz, Jordan; Gouterman, Vadim, Method and apparatus for performing parallel routing using a multi-threaded routing procedure.
  23. Betz, Vaughn; Swartz, Jordan; Gouterman, Vadim, Method and apparatus for performing parallel routing using a multi-threaded routing procedure.
  24. Betz, Vaughn; Swartz, Jordan; Gouterman, Vadim, Method and apparatus for performing parallel routing using a multi-threaded routing procedure.
  25. Khare, Manoj; Kumar, Akhilesh; Tan, Sin Sim, Method and apparatus for preventing starvation in a multi-node architecture.
  26. Manoj Khare ; Akhilesh Kumar, Method and apparatus for preventing starvation in a multi-node architecture.
  27. Khare,Manoj; Briggs,Faye A.; Kumar,Akhilesh; Looi,Lily P.; Cheng,Kai, Method and apparatus for reducing memory latency in a cache coherent multi-node architecture.
  28. Baxter, Glenn A.; Gan, Andy H., Method and apparatus for timing management in a converted design.
  29. Baxter, Glenn A.; Gan, Andy H., Method and apparatus for timing management in a converted design.
  30. Palumbo,Joseph J., Method for identification of sub-optimally placed circuits.
  31. Ghosh Pradiptya, Method for routing conductive paths in an integrated circuit.
  32. Gasanov Elyar E.,RUX ; Scepanovic Ranko ; Raspopovic Pedja ; Andreev Alexander E., Net routing using basis element decomposition.
  33. Gan Andy H. ; Baxter Glenn A., Place-holding library elements for defining routing paths.
  34. Majid Sarrafzadeh ; Lawrence Pileggi ; Sharad Malik ; Feroze Peshotan Taraporevala ; Abhijeet Chakraborty ; Gary K. Yeap ; Salil R. Raje ; Lilly Shieh ; Douglas B. Boyle ; Dennis Yamamoto, Placement method for integrated circuit design using topo-clustering.
  35. Sarrafzadeh, Majid; Pileggi, Lawrence; Malik, Sharad; Taraporevala, Feroze Peshotan; Chakraborty, Abhijeet; Yeap, Gary K.; Raje, Salil R.; Shieh, Lilly; Boyle, Douglas B.; Yamamoto, Dennis, Placement method for integrated circuit design using topo-clustering.
  36. Teig,Steven; Buset,Oscar; Jacques,Etienne; Caldwell,Andrew; Frankle,Jonathan, Routing method and apparatus.
  37. Kerzendorf,Werner; K철hler,Thomas; Langmeier,Andreas; Lohmiller,Winfried, Sensor system and method for determining system states.
  38. Alpert,Charles Jay; Nam,Gi Joon; Villarrubia,Paul Gerard; Yildiz,Mehmet Can, Stability metrics for placement to quantify the stability of placement algorithms.
  39. Howard, Gregory Eric; Tran, Andy Quang; Fan, Yanli; Muth, Kartheinz, System and method of crossover determination in differential pair and bondwire pairs to minimize crosstalk.
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